Add simulation-time width assertions to SV interfaces. #128

2025-04-11 21:14:15 -07:00
parent 48ae215eda
commit b95ba354c3
9 changed files with 61 additions and 0 deletions
--- a/src/peakrdl_regblock/cpuif/avalon/init.py
+++ b/src/peakrdl_regblock/cpuif/avalon/init.py
@@ -3,6 +3,7 @@ from ...utils import clog2

 class Avalon_Cpuif(CpuifBase):
    template_path = "avalon_tmpl.sv"
+    is_interface = True

    @property
    def port_declaration(self) -> str:
@@ -17,6 +18,8 @@ class Avalon_Cpuif(CpuifBase):
        return self.addr_width - clog2(self.data_width_bytes)

 class Avalon_Cpuif_flattened(Avalon_Cpuif):
+    is_interface = False
+
    @property
    def port_declaration(self) -> str:
        lines = [