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fix wavedrom json

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This commit is contained in:
Alex Mykyta
2022-02-21 22:33:54 -08:00
parent c3bfc2d416
commit bb8ae0d94f
5 changed files with 130 additions and 125 deletions
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6
docs/conf.py
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@@ -10,9 +10,9 @@
# add these directories to sys.path here. If the directory is relative to the # add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here. # documentation root, use os.path.abspath to make it absolute, like shown here.
# #
# import os import os
# import sys import sys
# sys.path.insert(0, os.path.abspath('.')) sys.path.insert(0, os.path.abspath('..'))
import datetime import datetime

108
docs/cpuif/internal_protocol.rst
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@@ -93,34 +93,34 @@ Both are valid and CPU interface logic shall be designed to anticipate either.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p....'}, {'name': 'clk', 'wave': 'p....'},
{name: 'cpuif_req', wave: '010..'}, {'name': 'cpuif_req', 'wave': '010..'},
{name: 'cpuif_req_is_wr', wave: 'x2x..'}, {'name': 'cpuif_req_is_wr', 'wave': 'x2x..'},
{name: 'cpuif_addr', wave: 'x2x..', data: ['A']}, {'name': 'cpuif_addr', 'wave': 'x2x..', data: ['A']},
{}, {},
{name: 'cpuif_*_ack', wave: '010..'}, {'name': 'cpuif_*_ack', 'wave': '010..'},
{name: 'cpuif_*_err', wave: 'x2x..'}, {'name': 'cpuif_*_err', 'wave': 'x2x..'},
], ],
foot: { 'foot': {
text: "Zero-latency transfer" 'text': "Zero-latency transfer"
} }
} }
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p..|...'}, {'name': 'clk', 'wave': 'p..|...'},
{name: 'cpuif_req', wave: '010|...'}, {'name': 'cpuif_req', 'wave': '010|...'},
{name: 'cpuif_req_is_wr', wave: 'x2x|...'}, {'name': 'cpuif_req_is_wr', 'wave': 'x2x|...'},
{name: 'cpuif_addr', wave: 'x2x|...', data: ['A']}, {'name': 'cpuif_addr', 'wave': 'x2x|...', data: ['A']},
{}, {},
{name: 'cpuif_*_ack', wave: '0..|10.'}, {'name': 'cpuif_*_ack', 'wave': '0..|10.'},
{name: 'cpuif_*_err', wave: 'x..|2x.'}, {'name': 'cpuif_*_err', 'wave': 'x..|2x.'},
], ],
foot: { 'foot': {
text: "Transfer with non-zero latency" 'text': "Transfer with non-zero latency"
} }
} }
@@ -134,18 +134,18 @@ For brevity, only showing non-zero latency transfers.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p..|...'}, {'name': 'clk', 'wave': 'p..|...'},
{name: 'cpuif_req', wave: '010|...'}, {'name': 'cpuif_req', 'wave': '010|...'},
{name: 'cpuif_req_is_wr', wave: 'x0x|...'}, {'name': 'cpuif_req_is_wr', 'wave': 'x0x|...'},
{name: 'cpuif_addr', wave: 'x3x|...', data: ['A']}, {'name': 'cpuif_addr', 'wave': 'x3x|...', data: ['A']},
{}, {},
{name: 'cpuif_rd_ack', wave: '0..|10.'}, {'name': 'cpuif_rd_ack', 'wave': '0..|10.'},
{name: 'cpuif_rd_err', wave: 'x..|0x.'}, {'name': 'cpuif_rd_err', 'wave': 'x..|0x.'},
{name: 'cpuif_rd_data', wave: 'x..|5x.', data: ['D']}, {'name': 'cpuif_rd_data', 'wave': 'x..|5x.', data: ['D']},
], ],
foot: { 'foot': {
text: "Read Transaction" 'text': "Read Transaction"
} }
} }
@@ -153,18 +153,18 @@ For brevity, only showing non-zero latency transfers.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p..|...'}, {'name': 'clk', 'wave': 'p..|...'},
{name: 'cpuif_req', wave: '010|...'}, {'name': 'cpuif_req', 'wave': '010|...'},
{name: 'cpuif_req_is_wr', wave: 'x1x|...'}, {'name': 'cpuif_req_is_wr', 'wave': 'x1x|...'},
{name: 'cpuif_addr', wave: 'x3x|...', data: ['A']}, {'name': 'cpuif_addr', 'wave': 'x3x|...', data: ['A']},
{name: 'cpuif_wr_data', wave: 'x5x|...', data: ['D']}, {'name': 'cpuif_wr_data', 'wave': 'x5x|...', data: ['D']},
{}, {},
{name: 'cpuif_wr_ack', wave: '0..|10.'}, {'name': 'cpuif_wr_ack', 'wave': '0..|10.'},
{name: 'cpuif_wr_err', wave: 'x..|0x.'}, {'name': 'cpuif_wr_err', 'wave': 'x..|0x.'},
], ],
foot: { 'foot': {
text: "Write Transaction" 'text': "Write Transaction"
} }
} }
@@ -176,15 +176,15 @@ If the CPU interface supports it, read and write operations can be pipelined.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p......'}, {'name': 'clk', 'wave': 'p......'},
{name: 'cpuif_req', wave: '01..0..'}, {'name': 'cpuif_req', 'wave': '01..0..'},
{name: 'cpuif_req_is_wr', wave: 'x0..x..'}, {'name': 'cpuif_req_is_wr', 'wave': 'x0..x..'},
{name: 'cpuif_addr', wave: 'x333x..', data: ['A1', 'A2', 'A3']}, {'name': 'cpuif_addr', 'wave': 'x333x..', data: ['A1', 'A2', 'A3']},
{}, {},
{name: 'cpuif_rd_ack', wave: '0.1..0.'}, {'name': 'cpuif_rd_ack', 'wave': '0.1..0.'},
{name: 'cpuif_rd_err', wave: 'x.0..x.'}, {'name': 'cpuif_rd_err', 'wave': 'x.0..x.'},
{name: 'cpuif_rd_data', wave: 'x.555x.', data: ['D1', 'D2', 'D3']}, {'name': 'cpuif_rd_data', 'wave': 'x.555x.', data: ['D1', 'D2', 'D3']},
] ]
} }
@@ -208,15 +208,15 @@ In the following example, the regblock is configured such that:
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p.......'}, {'name': 'clk', 'wave': 'p.......'},
{name: 'cpuif_req', wave: '01.....0'}, {'name': 'cpuif_req', 'wave': '01.....0'},
{name: 'cpuif_req_is_wr', wave: 'x1.0.1.x'}, {'name': 'cpuif_req_is_wr', 'wave': 'x1.0.1.x'},
{name: 'cpuif_addr', wave: 'x33443.x', data: ['W1', 'W2', 'R1', 'R2', 'W3']}, {'name': 'cpuif_addr', 'wave': 'x33443.x', data: ['W1', 'W2', 'R1', 'R2', 'W3']},
{name: 'cpuif_req_stall_wr', wave: '0...1.0.'}, {'name': 'cpuif_req_stall_wr', 'wave': '0...1.0.'},
{}, {},
{name: 'cpuif_rd_ack', wave: '0...220.', data: ['R1', 'R2']}, {'name': 'cpuif_rd_ack', 'wave': '0...220.', data: ['R1', 'R2']},
{name: 'cpuif_wr_ack', wave: '0220..20', data: ['W1', 'W2', 'W3']}, {'name': 'cpuif_wr_ack', 'wave': '0220..20', data: ['W1', 'W2', 'W3']},
] ]
} }

5
docs/dev_notes/Validation Needed
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@@ -174,3 +174,8 @@ X Warn/error on any signal with cpuif_reset set, that is not in the top-level
- each regfile/addrmap/stride shall be aligned to the largest regwidth it encloses - each regfile/addrmap/stride shall be aligned to the largest regwidth it encloses
--> Should i promote this check to the compiler? At least as a warnable condition --> Should i promote this check to the compiler? At least as a warnable condition
Currently i think I only do the more stringent case of block alignment. Currently i think I only do the more stringent case of block alignment.
! Add warning for sticky race condition
stickybit and other similar situations generally should use hw precedence.
Emit a warning as appropriate
Or should this be a compiler warning??

108
docs/props/field.rst
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@@ -23,10 +23,10 @@ If set, field will get cleared back to zero after being written.
.. wavedrom:: .. wavedrom::
{signal: [ {'signal': [
{name: 'clk', wave: 'p.....'}, {'name': 'clk', 'wave': 'p.....'},
{name: '<swmod>', wave: '0.10..'}, {'name': '<swmod>', 'wave': '0.10..'},
{name: 'hwif_out..value', wave: '0..10.'} {'name': 'hwif_out..value', 'wave': '0..10.'}
]} ]}
sw sw
@@ -43,10 +43,10 @@ operation.
.. wavedrom:: .. wavedrom::
{signal: [ {'signal': [
{name: 'clk', wave: 'p....'}, {'name': 'clk', 'wave': 'p....'},
{name: 'hwif_in..next', wave: 'x.=x.', data: ['D']}, {'name': 'hwif_in..next', 'wave': 'x.=x.', data: ['D']},
{name: 'hwif_out..swacc', wave: '0.10.'} {'name': 'hwif_out..swacc', 'wave': '0.10.'}
]} ]}
@@ -59,10 +59,10 @@ field is being modified by software.
.. wavedrom:: .. wavedrom::
{signal: [ {'signal': [
{name: 'clk', wave: 'p.....'}, {'name': 'clk', 'wave': 'p.....'},
{name: 'hwif_out..value', wave: '=..=..', data: ['old', 'new']}, {'name': 'hwif_out..value', 'wave': '=..=..', data: ['old', 'new']},
{name: 'hwif_out..swmod', wave: '0.10..'} {'name': 'hwif_out..swmod', 'wave': '0.10..'}
]} ]}
@@ -141,12 +141,12 @@ If true, infers the existence of input signal: ``hwif_in..we``, ``hwif_in..wel``
.. wavedrom:: .. wavedrom::
{signal: [ {'signal': [
{name: 'clk', wave: 'p....'}, {'name': 'clk', 'wave': 'p....'},
{name: 'hwif_in..next', wave: 'x.=x.', data: ['D']}, {'name': 'hwif_in..next', 'wave': 'x.=x.', data: ['D']},
{name: 'hwif_in..we', wave: '0.10.',}, {'name': 'hwif_in..we', 'wave': '0.10.',},
{name: 'hwif_in..wel', wave: '1.01.',}, {'name': 'hwif_in..wel', 'wave': '1.01.',},
{name: '<field value>', wave: 'x..=.', data: ['D']} {'name': '<field value>', 'wave': 'x..=.', data: ['D']}
]} ]}
boolean boolean
@@ -216,14 +216,14 @@ asserted if the counter value is greater or equal to the threshold.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p......'}, {'name': 'clk', 'wave': 'p......'},
{name: 'hwif_in..incr', wave: '01...0.'}, {'name': 'hwif_in..incr', 'wave': '01...0.'},
{name: '<counter>', wave: '=.=3==..', data: [4,5,6,7,8,9]}, {'name': '<counter>', 'wave': '=.=3==..', data: [4,5,6,7,8,9]},
{name: 'hwif_out..incrthreshold', wave: '0..1....'} {'name': 'hwif_out..incrthreshold', 'wave': '0..1....'}
], ],
foot: { 'foot': {
text: "Example where incrthreshold = 6" 'text': "Example where incrthreshold = 6"
} }
} }
@@ -272,14 +272,14 @@ the counter is about to wrap.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p.......'}, {'name': 'clk', 'wave': 'p.......'},
{name: 'hwif_in..incr', wave: '0101010.'}, {'name': 'hwif_in..incr', 'wave': '0101010.'},
{name: '<counter>', wave: '=.=.=.=.', data: [14,15,0,1]}, {'name': '<counter>', 'wave': '=.=.=.=.', data: [14,15,0,1]},
{name: 'hwif_out..overflow', wave: '0..10...'} {'name': 'hwif_out..overflow', 'wave': '0..10...'}
], ],
foot: { 'foot': {
text: "A 4-bit counter overflowing" 'text': "A 4-bit counter overflowing"
} }
} }
@@ -322,14 +322,14 @@ asserted if the counter value is less than or equal to the threshold.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p......'}, {'name': 'clk', 'wave': 'p......'},
{name: 'hwif_in..decr', wave: '01...0.'}, {'name': 'hwif_in..decr', 'wave': '01...0.'},
{name: '<counter>', wave: '=.=3==..', data: [9,8,7,6,5,4]}, {'name': '<counter>', 'wave': '=.=3==..', data: [9,8,7,6,5,4]},
{name: 'hwif_out..decrthreshold', wave: '0..1....'} {'name': 'hwif_out..decrthreshold', 'wave': '0..1....'}
], ],
foot: { 'foot': {
text: "Example where incrthreshold = 7" 'text': "Example where incrthreshold = 7"
} }
} }
@@ -377,14 +377,14 @@ the counter is about to wrap.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p.......'}, {'name': 'clk', 'wave': 'p.......'},
{name: 'hwif_in..decr', wave: '0101010.'}, {'name': 'hwif_in..decr', 'wave': '0101010.'},
{name: '<counter>', wave: '=.=.=.=.', data: [1,0,15,14]}, {'name': '<counter>', 'wave': '=.=.=.=.', data: [1,0,15,14]},
{name: 'hwif_out..underflow', wave: '0..10...'} {'name': 'hwif_out..underflow', 'wave': '0..10...'}
], ],
foot: { 'foot': {
text: "A 4-bit counter underflowing" 'text': "A 4-bit counter underflowing"
} }
} }
@@ -484,10 +484,10 @@ The waveform below demonstrates a level-sensitive interrupt:
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p.....'}, {'name': 'clk', 'wave': 'p.....'},
{name: 'hwif_in..next', wave: '010...'}, {'name': 'hwif_in..next', 'wave': '010...'},
{name: '<field value>', wave: '0.1...'} {'name': '<field value>', 'wave': '0.1...'}
] ]
} }
@@ -503,10 +503,10 @@ field contents are cleared back to 0 by a software access.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p.....'}, {'name': 'clk', 'wave': 'p.....'},
{name: 'hwif_in..next', wave: '23.22.', data: [0,10,20,30]}, {'name': 'hwif_in..next', 'wave': '23.22.', data: [0,10,20,30]},
{name: '<field value>', wave: '2.3...', data: [0, 10]} {'name': '<field value>', 'wave': '2.3...', data: [0, 10]}
] ]
} }

28
docs/props/rhs_props.rst
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@@ -100,14 +100,14 @@ at its saturation value.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p......'}, {'name': 'clk', 'wave': 'p......'},
{name: 'hwif_in..decr', wave: '0101010'}, {'name': 'hwif_in..decr', 'wave': '0101010'},
{name: '<counter>', wave: '=.=....', data: [1,0]}, {'name': '<counter>', 'wave': '=.=....', data: [1,0]},
{name: '<decrsaturate>', wave: '0.1....'} {'name': '<decrsaturate>', 'wave': '0.1....'}
], ],
foot: { 'foot': {
text: "A 4-bit counter saturating" 'text': "A 4-bit counter saturating"
} }
} }
@@ -147,14 +147,14 @@ at its saturation value.
.. wavedrom:: .. wavedrom::
{ {
signal: [ 'signal': [
{name: 'clk', wave: 'p......'}, {'name': 'clk', 'wave': 'p......'},
{name: 'hwif_in..incr', wave: '0101010'}, {'name': 'hwif_in..incr', 'wave': '0101010'},
{name: '<counter>', wave: '=.=....', data: [14,15]}, {'name': '<counter>', 'wave': '=.=....', data: [14,15]},
{name: '<incrsaturate>', wave: '0.1....'} {'name': '<incrsaturate>', 'wave': '0.1....'}
], ],
foot: { 'foot': {
text: "A 4-bit counter saturating" 'text': "A 4-bit counter saturating"
} }
} }