bslathi19/PeakRDL-regblock
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fix: a typo in SV template

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motchy
2024-03-10 23:44:29 +09:00
committed by Alex Mykyta
parent 0d39774d22
commit be8d84bba0
1 changed files with 1 additions and 1 deletions
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src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
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@@ -12,7 +12,7 @@ logic [{{cpuif.data_width_bytes-1}}:0] axil_wstrb;
logic axil_aw_accept; logic axil_aw_accept;
logic axil_resp_acked; logic axil_resp_acked;
// Transaction request accpetance // Transaction request acceptance
always_ff {{get_always_ff_event(cpuif.reset)}} begin always_ff {{get_always_ff_event(cpuif.reset)}} begin
if({{get_resetsignal(cpuif.reset)}}) begin if({{get_resetsignal(cpuif.reset)}}) begin
axil_prev_was_rd <= '0; axil_prev_was_rd <= '0;