diff --git a/docs/cpuif/introduction.rst b/docs/cpuif/introduction.rst
index 459da54..47f55ff 100644
--- a/docs/cpuif/introduction.rst
+++ b/docs/cpuif/introduction.rst
@@ -25,9 +25,12 @@ only include the local offset.
 For example, consider a fictional AXI4-Lite device that:
 
 - Consumes 4 kB of address space (``0x000``-``0xFFF``).
-- The device is instantiated in your system at global address ``0x80_0000``-``0x80_0FFF``.
+- The device is instantiated in your system at global address range ``0x30_0000 - 0x50_0FFF``.
 - After decoding transactions destined to the device, the system interconnect shall
   ensure that AxADDR values are presented to the device as relative addresses - within
   the range of ``0x000``-``0xFFF``.
 - If care is taken to align the global address offset to the size of the device,
   creating a relative address is as simple as pruning down address bits.
+
+By default, the bit-width of the address bus will be the minimum size to span the contents
+of the register block. If needed, the address width can be overridden to a larger range.
diff --git a/src/peakrdl_regblock/__about__.py b/src/peakrdl_regblock/__about__.py
index 3e2f46a..61fb31c 100644
--- a/src/peakrdl_regblock/__about__.py
+++ b/src/peakrdl_regblock/__about__.py
@@ -1 +1 @@
-__version__ = "0.9.0"
+__version__ = "0.10.0"
diff --git a/src/peakrdl_regblock/__peakrdl__.py b/src/peakrdl_regblock/__peakrdl__.py
index eaf6543..2ce1fa4 100644
--- a/src/peakrdl_regblock/__peakrdl__.py
+++ b/src/peakrdl_regblock/__peakrdl__.py
@@ -88,6 +88,15 @@ class Exporter:
             help="Generate a HWIF report file"
         )
 
+        arg_group.add_argument(
+            "--addr-width",
+            type=int,
+            default=None,
+            help="""Override the CPU interface's address width. By default,
+            address width is sized to the contents of the regblock.
+            """
+        )
+
 
     def do_export(self, top_node: 'AddrmapNode', options: 'argparse.Namespace') -> None:
         x = RegblockExporter()
@@ -101,4 +110,5 @@ class Exporter:
             retime_read_fanin=options.rt_read_fanin,
             retime_read_response=options.rt_read_response,
             generate_hwif_report=options.hwif_report,
+            address_width=options.addr_width,
         )
diff --git a/src/peakrdl_regblock/exporter.py b/src/peakrdl_regblock/exporter.py
index 40f1395..474920a 100644
--- a/src/peakrdl_regblock/exporter.py
+++ b/src/peakrdl_regblock/exporter.py
@@ -1,5 +1,5 @@
 import os
-from typing import Union, Any, Type
+from typing import Union, Any, Type, Optional
 
 import jinja2 as jj
 from systemrdl.node import AddrmapNode, RootNode
@@ -98,14 +98,18 @@ class RegblockExporter:
 
             Enabling this option will increase read transfer latency by 1 clock cycle.
         generate_hwif_report: bool
-            If set, generates a hwif report that can help understand the structure
-            of the hwif_in and hwif_out structures.
+            If set, generates a hwif report that can help designers understand
+            the contents of the ``hwif_in`` and ``hwif_out`` structures.
+        address_width: int
+            Override the CPU interface's address width. By default, address width
+            is sized to the contents of the regblock.
         """
         # If it is the root node, skip to top addrmap
         if isinstance(node, RootNode):
             self.top_node = node.top
         else:
             self.top_node = node
+        msg = self.top_node.env.msg
 
 
         cpuif_cls = kwargs.pop("cpuif_cls", None) or APB4_Cpuif # type: Type[CpuifBase]
@@ -113,6 +117,7 @@ class RegblockExporter:
         package_name = kwargs.pop("package_name", None) or (module_name + "_pkg") # type: str
         reuse_hwif_typedefs = kwargs.pop("reuse_hwif_typedefs", True) # type: bool
         generate_hwif_report = kwargs.pop("generate_hwif_report", False) # type: bool
+        user_addr_width = kwargs.pop("address_width", None) # type: Optional[int]
 
         # Pipelining options
         retime_read_fanin = kwargs.pop("retime_read_fanin", False) # type: bool
@@ -129,6 +134,12 @@ class RegblockExporter:
         if retime_read_response:
             self.min_read_latency += 1
 
+        addr_width = self.top_node.size.bit_length()
+        if user_addr_width is not None:
+            if user_addr_width < addr_width:
+                msg.fatal(f"User-specified address width shall be greater than {addr_width}.")
+            addr_width = user_addr_width
+
         # Scan the design for pre-export information
         scanner = DesignScanner(self)
         scanner.do_scan()
@@ -144,7 +155,7 @@ class RegblockExporter:
             self,
             cpuif_reset=self.top_node.cpuif_reset,
             data_width=scanner.cpuif_data_width,
-            addr_width=self.top_node.size.bit_length()
+            addr_width=addr_width
         )
         self.hwif = Hwif(
             self,