Add taxi apb

src/peakrdl_regblock/__about__.py

@@ -1,2 +1,2 @@
-version_info = (1, 2, 0)
+version_info = (1, 3, 0)
 __version__ = ".".join([str(n) for n in version_info])

src/peakrdl_regblock/__peakrdl__.py

@@ -7,7 +7,7 @@ from peakrdl.config import schema
 from peakrdl.plugins.entry_points import get_entry_points
 
 from .exporter import RegblockExporter
-from .cpuif import CpuifBase, apb3, apb4, axi4lite, passthrough, avalon, obi
+from .cpuif import CpuifBase, apb3, apb4, taxi_apb, axi4lite, passthrough, avalon, obi
 from .udps import ALL_UDPS
 
 if TYPE_CHECKING:
@@ -36,6 +36,7 @@ class Exporter(ExporterSubcommandPlugin):
             "apb3-flat": apb3.APB3_Cpuif_flattened,
             "apb4": apb4.APB4_Cpuif,
             "apb4-flat": apb4.APB4_Cpuif_flattened,
+            "taxi-apb" : taxi_apb.TaxiAPB_Cpuif,
             "axi4-lite": axi4lite.AXI4Lite_Cpuif,
             "axi4-lite-flat": axi4lite.AXI4Lite_Cpuif_flattened,
             "avalon-mm": avalon.Avalon_Cpuif,

src/peakrdl_regblock/cpuif/taxi_apb/__init__.py

@@ -0,0 +1,12 @@
+from ..base import CpuifBase
+
+class TaxiAPB_Cpuif(CpuifBase):
+    template_path = "taxi_apb_tmpl.sv"
+    is_interface = True
+
+    @property
+    def port_declaration(self) -> str:
+        return "taxi_apb_if.slv s_apb"
+
+    def signal(self, name:str) -> str:
+        return "s_apb." + name

src/peakrdl_regblock/cpuif/taxi_apb/taxi_apb_tmpl.sv

@@ -0,0 +1,51 @@
+{%- if cpuif.is_interface -%}
+`ifndef SYNTHESIS
+    initial begin
+        assert_bad_addr_width: assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("paddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
+        assert_bad_data_width: assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
+    end
+`endif
+
+{% endif -%}
+
+// Request
+logic is_active;
+always_ff {{get_always_ff_event(cpuif.reset)}} begin
+    if({{get_resetsignal(cpuif.reset)}}) begin
+        is_active <= '0;
+        cpuif_req <= '0;
+        cpuif_req_is_wr <= '0;
+        cpuif_addr <= '0;
+        cpuif_wr_data <= '0;
+        cpuif_wr_biten <= '0;
+    end else begin
+        if(~is_active) begin
+            if({{cpuif.signal("psel")}}) begin
+                is_active <= '1;
+                cpuif_req <= '1;
+                cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
+                {%- if cpuif.data_width_bytes == 1 %}
+                cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
+                {%- else %}
+                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
+                {%- endif %}
+                cpuif_wr_data <= {{cpuif.signal("pwdata")}};
+                for(int i=0; i<{{cpuif.data_width_bytes}}; i++) begin
+                    cpuif_wr_biten[i*8 +: 8] <= {8{ {{-cpuif.signal("pstrb")}}[i]}};
+                end
+            end
+        end else begin
+            cpuif_req <= '0;
+            if(cpuif_rd_ack || cpuif_wr_ack) begin
+                is_active <= '0;
+            end
+        end
+    end
+end
+
+// Response
+assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;
+assign {{cpuif.signal("prdata")}} = cpuif_rd_data;
+assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_wr_err;