Rework cpuif to support transaction pipelining. Add more docs. update simulator

peakrdl/regblock/cpuif/passthrough/__init__.py

@@ -10,6 +10,8 @@ class PassthroughCpuif(CpuifBase):
             "input wire s_cpuif_req_is_wr",
             f"input wire [{self.addr_width-1}:0] s_cpuif_addr",
             f"input wire [{self.data_width-1}:0] s_cpuif_wr_data",
+            "output wire s_cpuif_req_stall_wr",
+            "output wire s_cpuif_req_stall_rd",
             "output wire s_cpuif_rd_ack",
             "output wire s_cpuif_rd_err",
             f"output wire [{self.data_width-1}:0] s_cpuif_rd_data",

peakrdl/regblock/cpuif/passthrough/passthrough_tmpl.sv

@@ -2,6 +2,8 @@ assign cpuif_req = s_cpuif_req;
 assign cpuif_req_is_wr = s_cpuif_req_is_wr;
 assign cpuif_addr = s_cpuif_addr;
 assign cpuif_wr_data = s_cpuif_wr_data;
+assign s_cpuif_req_stall_wr = cpuif_req_stall_wr;
+assign s_cpuif_req_stall_rd = cpuif_req_stall_rd;
 assign s_cpuif_rd_ack = cpuif_rd_ack;
 assign s_cpuif_rd_err = cpuif_rd_err;
 assign s_cpuif_rd_data = cpuif_rd_data;

peakrdl/regblock/exporter.py

@@ -76,6 +76,12 @@ class RegblockExporter:
         if kwargs:
             raise TypeError("got an unexpected keyword argument '%s'" % list(kwargs.keys())[0])
 
+        min_read_latency = 0
+        min_write_latency = 0
+        if retime_read_fanin:
+            min_read_latency += 1
+        if retime_read_response:
+            min_read_latency += 1
 
         # Scan the design for any unsupported features
         # Also collect pre-export information
@@ -114,6 +120,8 @@ class RegblockExporter:
             "readback": self.readback,
             "get_always_ff_event": lambda resetsignal : get_always_ff_event(self.dereferencer, resetsignal),
             "retime_read_response": retime_read_response,
+            "min_read_latency": min_read_latency,
+            "min_write_latency": min_write_latency,
         }
 
         # Write out design

peakrdl/regblock/module_tmpl.sv

@@ -24,6 +24,8 @@ module {{module_name}} (
     logic cpuif_req_is_wr;
     logic [{{cpuif.addr_width-1}}:0] cpuif_addr;
     logic [{{cpuif.data_width-1}}:0] cpuif_wr_data;
+    logic cpuif_req_stall_wr;
+    logic cpuif_req_stall_rd;
 
     logic cpuif_rd_ack;
     logic cpuif_rd_err;
@@ -34,6 +36,40 @@ module {{module_name}} (
 
     {{cpuif.get_implementation()|indent}}
 
+{% if min_read_latency == min_write_latency %}
+    // Read & write latencies are balanced. Stalls not required
+    assign cpuif_req_stall_rd = '0;
+    assign cpuif_req_stall_wr = '0;
+{%- elif min_read_latency > min_write_latency %}
+    // Read latency > write latency. May need to delay next write that follows a read
+    logic [{{min_read_latency - min_write_latency - 1}}:0] cpuif_req_stall_sr;
+    always_ff {{get_always_ff_event(cpuif.reset)}} begin
+        if({{get_resetsignal(cpuif.reset)}}) begin
+            cpuif_req_stall_sr <= '0;
+        end else if(cpuif_req && !cpuif_req_is_wr) begin
+            cpuif_req_stall_sr <= '1;
+        end else begin
+            cpuif_req_stall_sr <= (cpuif_req_stall_sr >> 'd1);
+        end
+    end
+    assign cpuif_req_stall_rd = '0;
+    assign cpuif_req_stall_wr = cpuif_req_stall_sr[0];
+{%- else %}
+    // Write latency > read latency. May need to delay next read that follows a write
+    logic [{{min_write_latency - min_read_latency - 1}}:0] cpuif_req_stall_sr;
+    always_ff {{get_always_ff_event(cpuif.reset)}} begin
+        if({{get_resetsignal(cpuif.reset)}}) begin
+            cpuif_req_stall_sr <= '0;
+        end else if(cpuif_req && cpuif_req_is_wr) begin
+            cpuif_req_stall_sr <= '1;
+        end else begin
+            cpuif_req_stall_sr <= (cpuif_req_stall_sr >> 'd1);
+        end
+    end
+    assign cpuif_req_stall_rd = cpuif_req_stall_sr[0];
+    assign cpuif_req_stall_wr = '0;
+{%- endif %}
+
     //--------------------------------------------------------------------------
     // Address Decode
     //--------------------------------------------------------------------------
@@ -47,15 +83,15 @@ module {{module_name}} (
         {{address_decode.get_implementation()|indent(8)}}
     end
 
-    // Writes are always granted with no error response
-    assign cpuif_wr_ack = cpuif_req & cpuif_req_is_wr;
-    assign cpuif_wr_err = '0;
-
     // Pass down signals to next stage
     assign decoded_req = cpuif_req;
     assign decoded_req_is_wr = cpuif_req_is_wr;
     assign decoded_wr_data = cpuif_wr_data;
 
+    // Writes are always granted with no error response
+    assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
+    assign cpuif_wr_err = '0;
+
     //--------------------------------------------------------------------------
     // Field logic
     //--------------------------------------------------------------------------