Rework cpuif to support transaction pipelining. Add more docs. update simulator

2022-02-13 17:25:31 -08:00
parent de5eecf0e7
commit d0ba488904
21 changed files with 493 additions and 68 deletions
--- a/peakrdl/regblock/cpuif/passthrough/init.py
+++ b/peakrdl/regblock/cpuif/passthrough/init.py
@@ -10,6 +10,8 @@ class PassthroughCpuif(CpuifBase):
            "input wire s_cpuif_req_is_wr",
            f"input wire [{self.addr_width-1}:0] s_cpuif_addr",
            f"input wire [{self.data_width-1}:0] s_cpuif_wr_data",
+            "output wire s_cpuif_req_stall_wr",
+            "output wire s_cpuif_req_stall_rd",
            "output wire s_cpuif_rd_ack",
            "output wire s_cpuif_rd_err",
            f"output wire [{self.data_width-1}:0] s_cpuif_rd_data",