Add signed/fixedpoint properties (#140)

* declared intwidth, fracwidth, and is_signed UDPs

* fix boolean type name in UDP definition

* generate hwif fields with fixedpoint indices

* make "counter" and "encode" properties mutualy exclusive with signed/fixedpoint

* add signed/unsigned to hwif

* improved fixedpoint error messages, added validation tests

* added fixedpoint tests

* fixedpoint/signed not allowed for signal components

* added signed/fixedpoint UDP docs

* handle single-bit fixedpoint numbers

* fix too many positional arguments lint

* changed spelling of fixedpoint to fixed-point

* use "logic" in place of "unsigned logic"

* split signed and fixedpoint docs, added examples

* allow enums with is_signed=false

* split signed and fixedpoint implementations

* assorted nits picked

* updated is_signed validation unit test

tests/test_fixedpoint/regblock.rdl

@@ -0,0 +1,39 @@
+addrmap top {
+    default accesswidth = 64;
+    default regwidth = 64;
+    reg {
+        field {
+            sw = rw; hw = r;
+            intwidth = 8;
+            fracwidth = 8;
+        } f_Q8_8[16] = 0;
+        field {
+            sw = r; hw = w;
+            intwidth = 32;
+        } f_Q32_n12[20];
+        field {
+            sw = rw; hw = r;
+            fracwidth = 32;
+            is_signed;
+        } f_SQn8_32[24] = 0;
+        field {
+            sw = rw; hw = r;
+            fracwidth = 7;
+            is_signed;
+        } f_SQn6_7 = 0;
+    } r1 @ 0x0;
+
+    reg {
+        field {
+            sw = r; hw = w;
+            is_signed;
+        } f_signed[16];
+        field {
+            sw = rw; hw = r;
+            is_signed = false;
+        } f_unsigned[16] = 0;
+        field {
+            sw = r; hw = w;
+        } f_no_sign[16];
+    } r2 @ 0x8;
+};

tests/test_fixedpoint/tb_template.sv

@@ -0,0 +1,77 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // set all fields to all 1s
+    cb.hwif_in.r1.f_Q32_n12.next <= '1;
+    cb.hwif_in.r2.f_signed.next <= '1;
+    cb.hwif_in.r2.f_no_sign.next <= '1;
+    cpuif.write('h0, 64'hFFFF_FFFF_FFFF_FFFF);
+    cpuif.write('h8, 64'hFFFF_FFFF_FFFF_FFFF);
+    @cb;
+
+    // Q8.8
+    // verify bit range
+    assert(cb.hwif_out.r1.f_Q8_8.value[7:-8] == '1);
+    // verify bit width
+    assert($size(cb.hwif_out.r1.f_Q8_8.value) == 16);
+    // verfy unsigned
+    assert(cb.hwif_out.r1.f_Q8_8.value > 0);
+
+    // Q32.-12
+    // verify bit range
+    assert(cb.hwif_in.r1.f_Q32_n12.next[31:12] == '1);
+    // verify bit width
+    assert($size(cb.hwif_in.r1.f_Q32_n12.next) == 20);
+    // verify unsigned
+    assert(cb.hwif_in.r1.f_Q32_n12.next > 0);
+
+    // SQ-8.32
+    // verify bit range
+    assert(cb.hwif_out.r1.f_SQn8_32.value[-9:-32] == '1);
+    // verify bit width
+    assert($size(cb.hwif_out.r1.f_SQn8_32.value) == 24);
+    // verify signed
+    assert(cb.hwif_out.r1.f_SQn8_32.value < 0);
+
+    // SQ-6.7
+    // verify bit range
+    assert(cb.hwif_out.r1.f_SQn6_7.value[-7:-7] == '1);
+    // verify bit width
+    assert($size(cb.hwif_out.r1.f_SQn6_7.value) == 1);
+    // verify signed
+    assert(cb.hwif_out.r1.f_SQn6_7.value < 0);
+
+    // 16-bit signed integer
+    // verify bit range
+    assert(cb.hwif_in.r2.f_signed.next[15:0] == '1);
+    // verify bit width
+    assert($size(cb.hwif_in.r2.f_signed.next) == 16);
+    // verify signed
+    assert(cb.hwif_in.r2.f_signed.next < 0);
+
+    // 16-bit unsigned integer
+    // verify bit range
+    assert(cb.hwif_out.r2.f_unsigned.value[15:0] == '1);
+    // verify bit width
+    assert($size(cb.hwif_out.r2.f_unsigned.value) == 16);
+    // verify unsigned
+    assert(cb.hwif_out.r2.f_unsigned.value > 0);
+
+    // 16-bit field (no sign)
+    // verify bit range
+    assert(cb.hwif_in.r2.f_no_sign.next[15:0] == '1);
+    // verify bit width
+    assert($size(cb.hwif_in.r2.f_no_sign.next) == 16);
+    // verify unsigned (logic is unsigned in SV)
+    assert(cb.hwif_in.r2.f_no_sign.next > 0);
+
+    // verify readback
+    cpuif.assert_read('h0, 64'h1FFF_FFFF_FFFF_FFFF);
+    cpuif.assert_read('h8, 64'h0000_FFFF_FFFF_FFFF);
+
+{% endblock %}

tests/test_fixedpoint/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()

tests/test_validation_errors/fixedpoint_counter.rdl

@@ -0,0 +1,9 @@
+addrmap top {
+    reg {
+        field {
+            sw = rw; hw = r;
+            intwidth = 4;
+            counter;
+        } fixedpoint_counter[8] = 0;
+    } r1;
+};

tests/test_validation_errors/fixedpoint_enum.rdl

@@ -0,0 +1,15 @@
+addrmap top {
+    reg {
+        enum test_enum {
+            zero = 2'b00;
+            one = 2'b01;
+            two = 2'b10;
+            three = 2'b11;
+        };
+        field {
+            sw = rw; hw = r;
+            fracwidth = 0;
+            encode = test_enum;
+        } fixedpoint_enum[2] = 0;
+    } r1;
+};

tests/test_validation_errors/fixedpoint_inconsistent_width.rdl

@@ -0,0 +1,9 @@
+addrmap top {
+    reg {
+        field {
+            sw = rw; hw = r;
+            intwidth = 4;
+            fracwidth = 5;
+        } num[8] = 0;
+    } r1;
+};

tests/test_validation_errors/signed_counter.rdl

@@ -0,0 +1,14 @@
+addrmap top {
+    reg {
+        field {
+            sw = rw; hw = r;
+            is_signed = false;
+            counter;
+        } unsigned_counter[8] = 0;
+        field {
+            sw = rw; hw = r;
+            is_signed;
+            counter;
+        } signed_counter[8] = 0;
+    } r1;
+};

tests/test_validation_errors/signed_enum.rdl

@@ -0,0 +1,20 @@
+addrmap top {
+    reg {
+        enum test_enum {
+            zero = 2'b00;
+            one = 2'b01;
+            two = 2'b10;
+            three = 2'b11;
+        };
+        field {
+            sw = rw; hw = r;
+            is_signed = false;
+            encode = test_enum;
+        } unsigned_enum[2] = 0;
+        field {
+            sw = rw; hw = r;
+            is_signed;
+            encode = test_enum;
+        } signed_enum[2] = 0;
+    } r1;
+};

tests/test_validation_errors/testcase.py

@@ -89,3 +89,33 @@ class TestValidationErrors(BaseTestCase):
             "unsynth_reset2.rdl",
             "A field that uses an asynchronous reset cannot use a dynamic reset value. This is not synthesizable.",
         )
+
+    def test_fixedpoint_counter(self) -> None:
+        self.assert_validate_error(
+            "fixedpoint_counter.rdl",
+            "Fixed-point representations are not supported for counter fields.",
+        )
+
+    def test_fixedpoint_enum(self) -> None:
+        self.assert_validate_error(
+            "fixedpoint_enum.rdl",
+            "Fixed-point representations are not supported for fields encoded as an enum.",
+        )
+
+    def test_fixedpoint_inconsistent_width(self) -> None:
+        self.assert_validate_error(
+            "fixedpoint_inconsistent_width.rdl",
+            r"Number of integer bits \(4\) plus number of fractional bits \(5\) must be equal to the width of the component \(8\).",
+        )
+
+    def test_signed_counter(self) -> None:
+        self.assert_validate_error(
+            "signed_counter.rdl",
+            "The property is_signed=true is not supported for counter fields.",
+        )
+
+    def test_signed_enum(self) -> None:
+        self.assert_validate_error(
+            "signed_enum.rdl",
+            "The property is_signed=true is not supported for fields encoded as an enum."
+        )