readback!

doc/logbooks/000-Main-Logbook

@@ -84,22 +84,13 @@ Dev Todo list
     I shouldn't have to go to the hwif or whatever
     dereferencer should have all the query functions
 
-- readback mux
-
 - Start a sphinx docs thing
     I need to keep better track of everything!
     Diagrams of each layer in an architecture overview
     transcribe logbook into dev notes
 
-- Am i doing msb/lsb correctly?
-    bit ordering:
-        fields are always [msb:lsb]
-        but could be [low:high] or [high:low]
-    But how does this affect bus <-> field mapping though??
-        - [low:high] means that bit order gets swapped from the bus
-        - [high:low] means bit order is sliced naturally
-    DONE
-
+    Define strict interface expectations for each layer!
+    Including latency/etc
 
 endianness controls byte order of the CPU bus
     controls byteswap at the CPUIF layer
@@ -119,3 +110,7 @@ Do something about cpuif byte strobes?
         Generate these in the io struct? I forget what I decided
 
 - dereferencer has some remaining todos that depend on field logic
+
+- FIXME: cpuif reset inside top-level addrmap results in two input signals:
+    - one popped out to top
+    - another inside the input struct

doc/logbooks/Validation Needed

@@ -96,7 +96,9 @@ X If a node ispresent=true, and any of it's properties are a reference,
     y->we = y;
     ... it works, but should it be allowed? Seems like user-error
 
-
+! Signals marked as field_reset or cpuif_reset need to have activehigh/activelow
+  specified. (8.2.1-d states that activehigh/low does not have an implied default state if unset!)
+  Also aplies to signals referenced by fieldreset
 
 
 
@@ -109,19 +111,27 @@ List of stuff in case I forget.
     ! = No! exporter does not enforce this yet
 
 --------------------------------------------------------------------------------
+
+X Contents of target are all internal. No external regs
+
+X Does not contain any mem components
+
+X Warn/error on any signal with cpuif_reset set, that is not in the top-level
+    addrmap. At the very least, warn that it will be ignored
+
+
 ! "bridge" addrmap not supported
     export shall refuse to process an addrmap marked as a "bridge"
     Only need to check top-level. Compiler will enforce that child nodes arent bridges
 
-cpuif_resets
-    ! Warn/error on any signal with cpuif_reset set, that is not in the top-level
-        addrmap. At the very least, warn that it will be ignored
-
 ! async data signals
     Only supporting async signals if they are exclusively used in resets.
     Anyhting else declared as "async" shall be an error
     I have zero interest in implementing resynchronizers
 
+! Error if a property references a non-signal component, or property reference from
+    outside the export hierarchy
+
 ! regwidth/accesswidth is sane
     ! accesswidth == regwidth
         Enforce this for now. Dont feel like supporting fancy modes yet
@@ -135,9 +145,6 @@ cpuif_resets
         For now, probably limit to only allow the same regwidth everywhere?
 
 
-! Contents of target are all internal. No external regs
-! Does not contain any mem components
-
 ! Do not allow unaligned addresses
     All offsets & strides shall be a multiple of the regwidth used
 

doc/logbooks/template-layers/2-CPUIF

@@ -21,7 +21,7 @@ Downstream Signals:
             - cpuif_addr
                 Byte address
             - cpuif_wr_data
-            - cpuif_wr_bitstrb
+            - cpuif_wr_biten
                 per-bit strobes
                 some protocols may opt to tie this to all 1's
     - cpuif_rd_ack