readback!

peakrdl/regblock/module_tmpl.sv

@@ -19,20 +19,17 @@ module {{module_name}} (
         {{hwif.port_declaration|indent(8)}}
     );
 
-    localparam ADDR_WIDTH = {{addr_width}};
-    localparam DATA_WIDTH = {{data_width}};
-
     //--------------------------------------------------------------------------
     // CPU Bus interface logic
     //--------------------------------------------------------------------------
     logic cpuif_req;
     logic cpuif_req_is_wr;
-    logic [ADDR_WIDTH-1:0] cpuif_addr;
-    logic [DATA_WIDTH-1:0] cpuif_wr_data;
-    logic [DATA_WIDTH-1:0] cpuif_wr_bitstrb;
+    logic [{{cpuif.addr_width-1}}:0] cpuif_addr;
+    logic [{{cpuif.data_width-1}}:0] cpuif_wr_data;
+    logic [{{cpuif.data_width-1}}:0] cpuif_wr_biten;
 
     logic cpuif_rd_ack;
-    logic [DATA_WIDTH-1:0] cpuif_rd_data;
+    logic [{{cpuif.data_width-1}}:0] cpuif_rd_data;
     logic cpuif_rd_err;
 
     logic cpuif_wr_ack;
@@ -47,8 +44,8 @@ module {{module_name}} (
     decoded_reg_strb_t decoded_reg_strb;
     logic decoded_req;
     logic decoded_req_is_wr;
-    logic [DATA_WIDTH-1:0] decoded_wr_data;
-    logic [DATA_WIDTH-1:0] decoded_wr_bitstrb;
+    logic [{{cpuif.data_width-1}}:0] decoded_wr_data;
+    logic [{{cpuif.data_width-1}}:0] decoded_wr_biten;
 
     always_comb begin
         {{address_decode.get_implementation()|indent(8)}}
@@ -62,7 +59,7 @@ module {{module_name}} (
     assign decoded_req = cpuif_req;
     assign decoded_req_is_wr = cpuif_req_is_wr;
     assign decoded_wr_data = cpuif_wr_data;
-    assign decoded_wr_bitstrb = cpuif_wr_bitstrb;
+    assign decoded_wr_biten = cpuif_wr_biten;
 
     //--------------------------------------------------------------------------
     // Field logic
@@ -76,6 +73,27 @@ module {{module_name}} (
     //--------------------------------------------------------------------------
     // Readback
     //--------------------------------------------------------------------------
+    logic readback_err;
+    logic readback_done;
+    logic [{{cpuif.data_width-1}}:0] readback_data;
     {{readback.get_implementation()|indent}}
 
+{% if retime_read_response %}
+    always_ff {{get_always_ff_event(cpuif.reset)}} begin
+        if({{cpuif.reset.activehigh_identifier}}) begin
+            cpuif_rd_ack <= '0;
+            cpuif_rd_data <= '0;
+            cpuif_rd_err <= '0;
+        end else begin
+            cpuif_rd_ack <= readback_done;
+            cpuif_rd_data <= readback_data;
+            cpuif_rd_err <= readback_err;
+        end
+    end
+{% else %}
+    assign cpuif_rd_ack = readback_done;
+    assign cpuif_rd_data = readback_data;
+    assign cpuif_rd_err = readback_err;
+{% endif %}
+
 endmodule