readback!

peakrdl/regblock/readback/__init__.py

@@ -1,4 +1,5 @@
 from typing import TYPE_CHECKING
+import math
 
 from .generators import ReadbackAssignmentGenerator
 from ..utils import get_always_ff_event
@@ -8,8 +9,9 @@ if TYPE_CHECKING:
     from systemrdl.node import AddrmapNode
 
 class Readback:
-    def __init__(self, exp:'RegblockExporter'):
+    def __init__(self, exp:'RegblockExporter', do_fanin_stage: bool):
         self.exp = exp
+        self.do_fanin_stage = do_fanin_stage
 
     @property
     def top_node(self) -> 'AddrmapNode':
@@ -18,13 +20,49 @@ class Readback:
     def get_implementation(self) -> str:
         gen = ReadbackAssignmentGenerator(self.exp)
         array_assignments = gen.get_content(self.top_node)
+        array_size = gen.current_offset
+
+        # Enabling the fanin stage doesnt make sense if readback fanin is
+        # small. This also avoids pesky corner cases
+        if array_size < 4:
+            self.do_fanin_stage = False
 
         context = {
             "array_assignments" : array_assignments,
-            "array_size" : gen.current_offset,
+            "array_size" : array_size,
             "get_always_ff_event": get_always_ff_event,
-            "cpuif_reset": self.exp.cpuif_reset,
+            "cpuif": self.exp.cpuif,
+            "do_fanin_stage": self.do_fanin_stage,
         }
+
+        if self.do_fanin_stage:
+            # If adding a fanin pipeline stage, goal is to try to
+            # split the fanin path in the middle so that fanin into the stage
+            # and the following are roughly balanced.
+            fanin_target = math.sqrt(array_size)
+
+            # Size of fanin group to consume per fanin element
+            fanin_stride = math.floor(fanin_target)
+
+            # Number of array elements to reduce to.
+            # Round up to an extra element in case there is some residual
+            fanin_array_size = math.ceil(array_size / fanin_stride)
+
+            # leftovers are handled in an extra array element
+            fanin_residual_stride = array_size % fanin_stride
+
+            if fanin_residual_stride != 0:
+                # If there is a partial fanin element, reduce the number of
+                # loops performed in the bulk fanin stage
+                fanin_loop_iter = fanin_array_size - 1
+            else:
+                fanin_loop_iter = fanin_array_size
+
+            context['fanin_stride'] = fanin_stride
+            context['fanin_array_size'] = fanin_array_size
+            context['fanin_residual_stride'] = fanin_residual_stride
+            context['fanin_loop_iter'] = fanin_loop_iter
+
         template = self.exp.jj_env.get_template(
             "readback/templates/readback.sv"
         )

peakrdl/regblock/readback/templates/readback.sv

@@ -1,45 +1,68 @@
 {% if array_assignments is not none %}
-logic readback_err;
-logic readback_done;
-logic [DATA_WIDTH-1:0] readback_data;
-logic [DATA_WIDTH-1:0] readback_array[{{array_size}}];
-
+// Assign readback values to a flattened array
+logic [{{cpuif.data_width-1}}:0] readback_array[{{array_size}}];
 {{array_assignments}}
 
+{% if do_fanin_stage %}
+// fanin stage
+logic [31:0] readback_array_c[{{fanin_array_size}}];
+for(genvar g=0; g<{{fanin_loop_iter}}; g++) begin
+    always_comb begin
+        automatic logic [31:0] readback_data_var;
+        readback_data_var = '0;
+        for(int i=g*{{fanin_stride}}; i<((g+1)*{{fanin_stride}}); i++) readback_data_var |= readback_array[i];
+        readback_array_c[g] = readback_data_var;
+    end
+end
+{%- if fanin_residual_stride == 1 %}
+assign readback_array_c[{{fanin_array_size-1}}] = readback_array[{{array_size-1}}];
+{%- elif fanin_residual_stride > 1 %}
 always_comb begin
-    automatic logic [DATA_WIDTH-1:0] readback_data_var;
+    automatic logic [31:0] readback_data_var;
+    readback_data_var = '0;
+    for(int i={{(fanin_array_size-1) * fanin_stride}}; i<{{array_size-1}}; i++) readback_data_var |= readback_array[i];
+    readback_array_c[{{fanin_array_size-1}}] = readback_data_var;
+end
+{%- endif %}
+
+logic [31:0] readback_array_r[{{fanin_array_size}}];
+logic readback_done_r;
+always_ff @(posedge clk) begin
+    if(rst) begin
+        for(int i=0; i<{{fanin_array_size}}; i++) readback_array_r[i] <= '0;
+        readback_done_r <= '0;
+    end else begin
+        readback_array_r <= readback_array_c;
+        readback_done_r <= decoded_req & ~decoded_req_is_wr;
+    end
+end
+
+// Reduce the array
+always_comb begin
+    automatic logic [31:0] readback_data_var;
     readback_done = decoded_req & ~decoded_req_is_wr;
     readback_err = '0;
-
     readback_data_var = '0;
-    for(int i=0; i<{{array_size}}; i++) begin
-        readback_data_var |= readback_array[i];
-    end
+    for(int i=0; i<{{fanin_array_size}}; i++) readback_data_var |= readback_array_r[i];
     readback_data = readback_data_var;
 end
 
-always_ff {{get_always_ff_event(cpuif_reset)}} begin
-    if({{cpuif_reset.activehigh_identifier}}) begin
-        cpuif_rd_ack <= '0;
-        cpuif_rd_data <= '0;
-        cpuif_rd_err <= '0;
-    end else begin
-        cpuif_rd_ack <= readback_done;
-        cpuif_rd_data <= readback_data;
-        cpuif_rd_err <= readback_err;
-    end
+{%- else %}
+// Reduce the array
+always_comb begin
+    automatic logic [{{cpuif.data_width-1}}:0] readback_data_var;
+    readback_done = decoded_req & ~decoded_req_is_wr;
+    readback_err = '0;
+    readback_data_var = '0;
+    for(int i=0; i<{{array_size}}; i++) readback_data_var |= readback_array[i];
+    readback_data = readback_data_var;
 end
+{%- endif %}
 
 
 
 {%- else %}
-always_ff {{get_always_ff_event(cpuif_reset)}} begin
-    if({{cpuif_reset.activehigh_identifier}}) begin
-        cpuif_rd_ack <= '0;
-    end else begin
-        cpuif_rd_ack <= decoded_req & ~decoded_req_is_wr;
-    end
-end
-assign cpuif_rd_data = '0;
-assign cpuif_rd_err = '0;
+assign readback_done = decoded_req & ~decoded_req_is_wr;
+assign readback_data = '0;
+assign readback_err = '0;
 {% endif %}