bslathi19/PeakRDL-regblock
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Make remaining interrupt conditional predicates single-bit. #54

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Alex Mykyta
2023-07-19 20:17:46 -07:00
parent 18f8f358b2
commit da8ff4aaeb
1 changed files with 4 additions and 3 deletions
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7
src/peakrdl_regblock/field_logic/hw_interrupts.py
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@@ -44,7 +44,8 @@ class Stickybit(NextStateConditional):
) )
def get_predicate(self, field: 'FieldNode') -> str: def get_predicate(self, field: 'FieldNode') -> str:
return self.exp.hwif.get_input_identifier(field) F = self.exp.hwif.get_input_identifier(field)
return f"{F} != '0"
def get_assignments(self, field: 'FieldNode') -> List[str]: def get_assignments(self, field: 'FieldNode') -> List[str]:
I = self.exp.hwif.get_input_identifier(field) I = self.exp.hwif.get_input_identifier(field)
@@ -69,7 +70,7 @@ class PosedgeStickybit(NextStateConditional):
def get_predicate(self, field: 'FieldNode') -> str: def get_predicate(self, field: 'FieldNode') -> str:
I = self.exp.hwif.get_input_identifier(field) I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field) Iq = self.exp.field_logic.get_next_q_identifier(field)
return f"~{Iq} & {I}" return f"(~{Iq} & {I}) != '0"
def get_assignments(self, field: 'FieldNode') -> List[str]: def get_assignments(self, field: 'FieldNode') -> List[str]:
I = self.exp.hwif.get_input_identifier(field) I = self.exp.hwif.get_input_identifier(field)
@@ -95,7 +96,7 @@ class NegedgeStickybit(NextStateConditional):
def get_predicate(self, field: 'FieldNode') -> str: def get_predicate(self, field: 'FieldNode') -> str:
I = self.exp.hwif.get_input_identifier(field) I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field) Iq = self.exp.field_logic.get_next_q_identifier(field)
return f"{Iq} & ~{I}" return f"({Iq} & ~{I}) != '0"
def get_assignments(self, field: 'FieldNode') -> List[str]: def get_assignments(self, field: 'FieldNode') -> List[str]:
I = self.exp.hwif.get_input_identifier(field) I = self.exp.hwif.get_input_identifier(field)