bslathi19/PeakRDL-regblock
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Fixup test bitswap. mypy

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This commit is contained in:
Alex Mykyta
2024-12-18 22:04:12 -08:00
parent 11d9f65dff
commit e0295ae526
7 changed files with 43 additions and 34 deletions
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2
src/peakrdl_regblock/entry_points.py
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@@ -40,7 +40,7 @@ elif sys.version_info >= (3,8,0): # pragma: no cover
return dist.metadata["Name"] return dist.metadata["Name"]
else: # pragma: no cover else: # pragma: no cover
import pkg_resources # type: ignore import pkg_resources
def _get_entry_points(group_name: str) -> List[Tuple['EntryPoint', 'Distribution']]: def _get_entry_points(group_name: str) -> List[Tuple['EntryPoint', 'Distribution']]:
eps = [] eps = []

2
src/peakrdl_regblock/field_logic/sw_onread.py
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@@ -8,7 +8,7 @@ if TYPE_CHECKING:
from systemrdl.node import FieldNode from systemrdl.node import FieldNode
class _OnRead(NextStateConditional): class _OnRead(NextStateConditional):
onreadtype = None onreadtype = None # type: OnReadType
def is_match(self, field: 'FieldNode') -> bool: def is_match(self, field: 'FieldNode') -> bool:
return field.get_property('onread') == self.onreadtype return field.get_property('onread') == self.onreadtype

2
src/peakrdl_regblock/field_logic/sw_onwrite.py
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@@ -10,7 +10,7 @@ if TYPE_CHECKING:
# TODO: implement sw=w1 "write once" fields # TODO: implement sw=w1 "write once" fields
class _OnWrite(NextStateConditional): class _OnWrite(NextStateConditional):
onwritetype = None onwritetype = None # type: OnWriteType
def is_match(self, field: 'FieldNode') -> bool: def is_match(self, field: 'FieldNode') -> bool:
return field.is_sw_writable and field.get_property('onwrite') == self.onwritetype return field.is_sw_writable and field.get_property('onwrite') == self.onwritetype

12
src/peakrdl_regblock/forloop_generator.py
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@@ -1,7 +1,7 @@
from typing import TYPE_CHECKING, Optional, List, Union from typing import TYPE_CHECKING, Optional, List, Union
import textwrap import textwrap
from systemrdl.walker import RDLListener, RDLWalker from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
if TYPE_CHECKING: if TYPE_CHECKING:
from systemrdl.node import AddressableNode, Node from systemrdl.node import AddressableNode, Node
@@ -81,16 +81,18 @@ class RDLForLoopGenerator(ForLoopGenerator, RDLListener):
walker.walk(node, self, skip_top=True) walker.walk(node, self, skip_top=True)
return self.finish() return self.finish()
def enter_AddressableComponent(self, node: 'AddressableNode') -> None: def enter_AddressableComponent(self, node: 'AddressableNode') -> Optional[WalkerAction]:
if not node.is_array: if not node.is_array:
return return None
for dim in node.array_dimensions: for dim in node.array_dimensions:
self.push_loop(dim) self.push_loop(dim)
return None
def exit_AddressableComponent(self, node: 'AddressableNode') -> None: def exit_AddressableComponent(self, node: 'AddressableNode') -> Optional[WalkerAction]:
if not node.is_array: if not node.is_array:
return return None
for _ in node.array_dimensions: for _ in node.array_dimensions:
self.pop_loop() self.pop_loop()
return None

12
src/peakrdl_regblock/hwif/generators.py
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@@ -72,13 +72,13 @@ class InputStructGenerator_Hier(HWIFStructGenerator):
self.add_member("rd_data", self.hwif.ds.cpuif_data_width) self.add_member("rd_data", self.hwif.ds.cpuif_data_width)
self.add_member("wr_ack") self.add_member("wr_ack")
def enter_Addrmap(self, node: 'AddrmapNode') -> None: def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
super().enter_Addrmap(node) super().enter_Addrmap(node)
assert node.external assert node.external
self._add_external_block_members(node) self._add_external_block_members(node)
return WalkerAction.SkipDescendants return WalkerAction.SkipDescendants
def enter_Regfile(self, node: 'RegfileNode') -> None: def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
super().enter_Regfile(node) super().enter_Regfile(node)
if node.external: if node.external:
self._add_external_block_members(node) self._add_external_block_members(node)
@@ -137,7 +137,7 @@ class InputStructGenerator_Hier(HWIFStructGenerator):
# Multiple sub-words. Cannot generate a struct # Multiple sub-words. Cannot generate a struct
self.add_member("rd_data", width) self.add_member("rd_data", width)
def enter_Field(self, node: 'FieldNode') -> None: def enter_Field(self, node: 'FieldNode') -> Optional[WalkerAction]:
type_name = self.get_typdef_name(node) type_name = self.get_typdef_name(node)
self.push_struct(type_name, kwf(node.inst_name)) self.push_struct(type_name, kwf(node.inst_name))
@@ -175,7 +175,7 @@ class InputStructGenerator_Hier(HWIFStructGenerator):
# Implies a corresponding decrvalue input # Implies a corresponding decrvalue input
self.add_member('decrvalue', width) self.add_member('decrvalue', width)
def exit_Field(self, node: 'FieldNode') -> None: def exit_Field(self, node: 'FieldNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
@@ -199,13 +199,13 @@ class OutputStructGenerator_Hier(HWIFStructGenerator):
self.add_member("wr_data", self.hwif.ds.cpuif_data_width) self.add_member("wr_data", self.hwif.ds.cpuif_data_width)
self.add_member("wr_biten", self.hwif.ds.cpuif_data_width) self.add_member("wr_biten", self.hwif.ds.cpuif_data_width)
def enter_Addrmap(self, node: 'AddrmapNode') -> None: def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
super().enter_Addrmap(node) super().enter_Addrmap(node)
assert node.external assert node.external
self._add_external_block_members(node) self._add_external_block_members(node)
return WalkerAction.SkipDescendants return WalkerAction.SkipDescendants
def enter_Regfile(self, node: 'RegfileNode') -> None: def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
super().enter_Regfile(node) super().enter_Regfile(node)
if node.external: if node.external:
self._add_external_block_members(node) self._add_external_block_members(node)

38
src/peakrdl_regblock/struct_generator.py
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@@ -2,7 +2,7 @@ from typing import TYPE_CHECKING, Optional, List
import textwrap import textwrap
from collections import OrderedDict from collections import OrderedDict
from systemrdl.walker import RDLListener, RDLWalker from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
from .identifier_filter import kw_filter as kwf from .identifier_filter import kw_filter as kwf
@@ -140,31 +140,31 @@ class RDLStructGenerator(StructGenerator, RDLListener):
return self.finish() return self.finish()
def enter_Addrmap(self, node: 'AddrmapNode') -> None: def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
self.push_struct(kwf(node.inst_name), node.array_dimensions) self.push_struct(kwf(node.inst_name), node.array_dimensions)
def exit_Addrmap(self, node: 'AddrmapNode') -> None: def exit_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
def enter_Regfile(self, node: 'RegfileNode') -> None: def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
self.push_struct(kwf(node.inst_name), node.array_dimensions) self.push_struct(kwf(node.inst_name), node.array_dimensions)
def exit_Regfile(self, node: 'RegfileNode') -> None: def exit_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
def enter_Mem(self, node: 'MemNode') -> None: def enter_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
self.push_struct(kwf(node.inst_name), node.array_dimensions) self.push_struct(kwf(node.inst_name), node.array_dimensions)
def exit_Mem(self, node: 'MemNode') -> None: def exit_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
def enter_Reg(self, node: 'RegNode') -> None: def enter_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
self.push_struct(kwf(node.inst_name), node.array_dimensions) self.push_struct(kwf(node.inst_name), node.array_dimensions)
def exit_Reg(self, node: 'RegNode') -> None: def exit_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
def enter_Field(self, node: 'FieldNode') -> None: def enter_Field(self, node: 'FieldNode') -> Optional[WalkerAction]:
self.add_member(kwf(node.inst_name), node.width) self.add_member(kwf(node.inst_name), node.width)
#------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
@@ -228,33 +228,33 @@ class RDLFlatStructGenerator(FlatStructGenerator, RDLListener):
return self.finish() return self.finish()
def enter_Addrmap(self, node: 'AddrmapNode') -> None: def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
type_name = self.get_typdef_name(node) type_name = self.get_typdef_name(node)
self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions) self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions)
def exit_Addrmap(self, node: 'AddrmapNode') -> None: def exit_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
def enter_Regfile(self, node: 'RegfileNode') -> None: def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
type_name = self.get_typdef_name(node) type_name = self.get_typdef_name(node)
self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions) self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions)
def exit_Regfile(self, node: 'RegfileNode') -> None: def exit_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
def enter_Mem(self, node: 'MemNode') -> None: def enter_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
type_name = self.get_typdef_name(node) type_name = self.get_typdef_name(node)
self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions) self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions)
def exit_Mem(self, node: 'MemNode') -> None: def exit_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
def enter_Reg(self, node: 'RegNode') -> None: def enter_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
type_name = self.get_typdef_name(node) type_name = self.get_typdef_name(node)
self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions) self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions)
def exit_Reg(self, node: 'RegNode') -> None: def exit_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
self.pop_struct() self.pop_struct()
def enter_Field(self, node: 'FieldNode') -> None: def enter_Field(self, node: 'FieldNode') -> Optional[WalkerAction]:
self.add_member(kwf(node.inst_name), node.width) self.add_member(kwf(node.inst_name), node.width)

9
tests/lib/tb_base.sv
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@@ -3,7 +3,14 @@ module tb;
timeunit 10ps; timeunit 10ps;
timeprecision 1ps; timeprecision 1ps;
`define bitswap(x) ($bits(x))'({<<{x}}) class bitswap_cls #(W=1);
static function logic [W-1:0] bitswap(logic [W-1:0] x);
logic [W-1:0] result;
result = {<<{x}};
return result;
endfunction
endclass
`define bitswap(x) (bitswap_cls#($bits(x))::bitswap(x))
logic rst = '1; logic rst = '1;
logic clk = '0; logic clk = '0;