Add support for wide registers (where accesswidth < regwidth)
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@@ -18,18 +18,41 @@ Registers instantiated using the ``alias`` keyword are not supported yet.
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Unaligned Registers
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-------------------
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All address offsets & strides shall be a multiple of the accesswidth used. Specifically:
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All address offsets & strides shall be a multiple of the cpuif bus width used. Specifically:
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* Each register's address and array stride shall be aligned to it's accesswidth.
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* Each regfile or addrmap shall use an offset and stride that is a multiple of the largest accesswidth it encloses.
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* Bus width is inferred by the maximum accesswidth used in the regblock.
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* Each component's address and array stride shall be aligned to the bus width.
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Register width, Access width and CPUIF bus width
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------------------------------------------------
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To keep the initial architecture simpler, currently ``regwidth``, ``accesswidth``
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and the resulting CPU bus width has some limitations:
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Uniform accesswidth
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-------------------
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All registers within a register block shall use the same accesswidth.
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* All registers shall have ``regwidth`` == ``accesswidth``
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* ``regwidth`` shall be the same across all registers within the block being exported.
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One exception is that registers with regwidth that is narrower than the cpuif
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bus width are permitted, provided that their regwidth is equal to their accesswidth.
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I have plans to remove these restrictions and allow for more flexibility in the future.
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For example:
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.. code-block:: systemrdl
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// (Largest accesswidth used is 32, therefore the CPUIF bus width is 32)
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reg {
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regwidth = 32;
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accesswidth = 32;
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} reg_a @ 0x00; // OK. Regular 32-bit register
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reg {
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regwidth = 64;
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accesswidth = 32;
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} reg_b @ 0x08; // OK. "Wide" register of 64-bits, but is accessed using 32-bit subwords
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reg {
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regwidth = 8;
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accesswidth = 8;
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} reg_c @ 0x10; // OK. Is aligned to the cpuif bus width
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reg {
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regwidth = 32;
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accesswidth = 8;
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} bad_reg @ 0x14; // NOT OK. accesswidth conflicts with cpuif width
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