bslathi19/PeakRDL-regblock
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Add support for wide registers (where accesswidth < regwidth)

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Alex Mykyta
2022-10-12 20:44:22 -07:00
parent 21a4e5a41c
commit e07e7d26b2
18 changed files with 687 additions and 206 deletions
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4
src/peakrdl_regblock/dereferencer.py
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@@ -195,11 +195,11 @@ class Dereferencer:
raise NotImplementedError
def get_access_strobe(self, obj: Union[RegNode, FieldNode]) -> str:
def get_access_strobe(self, obj: Union[RegNode, FieldNode], reduce_substrobes: bool=True) -> str:
"""
Returns the Verilog string that represents the register's access strobe
"""
return self.address_decode.get_access_strobe(obj)
return self.address_decode.get_access_strobe(obj, reduce_substrobes)
def get_resetsignal(self, obj: Optional[SignalNode]) -> str:
"""