Add support for wide registers (where accesswidth < regwidth)

tests/test_structural_sw_rw/regblock.rdl

@@ -31,4 +31,14 @@ addrmap regblock {
     };
     subrf sub2[2] @ 0x2000 += 0x40;
     subreg r3 @ 0x2080;
+
+    reg {
+        field {} f1[19:12] = 0;
+        field {} f2[30:20] = 0;
+    } rw_reg @ 0x3000;
+
+    reg {
+        field {} f1[12:19] = 0;
+        field {} f2[20:30] = 0;
+    } rw_reg_lsb0 @ 0x3004;
 };

tests/test_structural_sw_rw/tb_template.sv

@@ -61,4 +61,20 @@
     assert(cb.hwif_out.r2.a.value == 'h0);
     assert(cb.hwif_out.r2.b.value == 'h0);
     assert(cb.hwif_out.r2.c.value == 'h0);
+
+    // rw_reg
+    cpuif.assert_read('h3000, 0);
+    cpuif.write('h3000, 'h4DEAB000);
+    @cb;
+    assert(cb.hwif_out.rw_reg.f1.value == 8'hAB);
+    assert(cb.hwif_out.rw_reg.f2.value == 11'h4DE);
+    cpuif.assert_read('h3000, 'h4DEAB000);
+
+    // rw_reg_lsb0
+    cpuif.assert_read('h3004, 0);
+    cpuif.write('h3004, 'h4DEAB000);
+    @cb;
+    assert({<<{cb.hwif_out.rw_reg_lsb0.f1.value}} == 8'hAB);
+    assert({<<{cb.hwif_out.rw_reg_lsb0.f2.value}} == 11'h4DE);
+    cpuif.assert_read('h3004, 'h4DEAB000);
 {% endblock %}

tests/test_structural_sw_rw/testcase.py

@@ -19,7 +19,7 @@ class TestSynth(SynthTestCase):
         self.run_synth()
 
 
-@pytest.mark.skipif(os.environ.get("STUB_SIMULATOR", False), reason="user skipped")
+@pytest.mark.skipif(os.environ.get("STUB_SIMULATOR", False) or os.environ.get("NO_XSIM", False), reason="user skipped")
 @parameterized_class(TEST_PARAMS)
 class TestVivado(SimTestCase):
     """