Add support for wide registers (where accesswidth < regwidth)

2022-10-12 20:44:22 -07:00
parent 21a4e5a41c
commit e07e7d26b2
18 changed files with 687 additions and 206 deletions
--- a/tests/test_structural_sw_rw/testcase.py
+++ b/tests/test_structural_sw_rw/testcase.py
@@ -19,7 +19,7 @@ class TestSynth(SynthTestCase):
        self.run_synth()


-@pytest.mark.skipif(os.environ.get("STUB_SIMULATOR", False), reason="user skipped")
+@pytest.mark.skipif(os.environ.get("STUB_SIMULATOR", False) or os.environ.get("NO_XSIM", False), reason="user skipped")
@parameterized_class(TEST_PARAMS)
 class TestVivado(SimTestCase):
    """