Add support for wide registers (where accesswidth < regwidth)

2022-10-12 20:44:22 -07:00
parent 21a4e5a41c
commit e07e7d26b2
18 changed files with 687 additions and 206 deletions
--- a/tests/test_wide_regs/testcase.py
+++ b/tests/test_wide_regs/testcase.py
@@ -0,0 +1,5 @@
+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()