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Rework interpretation of accesswidth/regwidth. accesswidth determines bus width

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Alex Mykyta
2022-09-12 21:09:52 -07:00
parent f3d932ccdf
commit e2d6fc1c60
3 changed files with 30 additions and 23 deletions
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7
docs/cpuif/introduction.rst
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@@ -7,6 +7,13 @@ When exporting a design, you can select from a variety of popular CPU interface
protocols. These are described in more detail in the pages that follow.
Bus Width
^^^^^^^^^
The CPU interface bus width is automatically determined from the contents of the
design being exported. The bus width is equal to the widest ``accesswidth``
encountered in the deisgn.
Addressing
^^^^^^^^^^

7
docs/limitations.rst
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@@ -18,10 +18,10 @@ Registers instantiated using the ``alias`` keyword are not supported yet.
Unaligned Registers
-------------------
All address offsets & strides shall be a multiple of the regwidth used. Specifically:
All address offsets & strides shall be a multiple of the accesswidth used. Specifically:
* Each register's address and array stride shall be aligned to it's regwidth.
* Each regfile or addrmap shall use an offset and stride that is a multiple of the largest regwidth it encloses.
* Each register's address and array stride shall be aligned to it's accesswidth.
* Each regfile or addrmap shall use an offset and stride that is a multiple of the largest accesswidth it encloses.
No partial writes
@@ -38,6 +38,5 @@ and the resulting CPU bus width has some limitations:
* All registers shall have ``regwidth`` == ``accesswidth``
* ``regwidth`` shall be the same across all registers within the block being exported.
* The CPU interface's bus width is statically determined by the ``regwidth`` used.
I have plans to remove these restrictions and allow for more flexibility in the future.