Rework interpretation of accesswidth/regwidth. accesswidth determines bus width

2022-09-12 21:09:52 -07:00
parent f3d932ccdf
commit e2d6fc1c60
3 changed files with 30 additions and 23 deletions
--- a/docs/cpuif/introduction.rst
+++ b/docs/cpuif/introduction.rst
@@ -7,6 +7,13 @@ When exporting a design, you can select from a variety of popular CPU interface
 protocols. These are described in more detail in the pages that follow.


+Bus Width
+^^^^^^^^^
+The CPU interface bus width is automatically determined from the contents of the
+design being exported. The bus width is equal to the widest ``accesswidth``
+encountered in the deisgn.
+
+
 Addressing
 ^^^^^^^^^^