Collapse hwif into one file
This commit is contained in:
Alex Mykyta
247
peakrdl/regblock/hwif.py
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247
peakrdl/regblock/hwif.py
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from typing import TYPE_CHECKING, Union, List
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from systemrdl.node import Node, SignalNode, FieldNode, AddressableNode
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from systemrdl.rdltypes import PropertyReference
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if TYPE_CHECKING:
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from .exporter import RegblockExporter
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class Hwif:
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"""
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Defines how the hardware input/output signals are generated:
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- Field outputs
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- Field inputs
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- Signal inputs (except those that are promoted to the top)
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"""
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def __init__(self, exporter: 'RegblockExporter', top_node: Node, package_name: str):
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self.exporter = exporter
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self.top_node = top_node
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self.package_name = package_name
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self.has_input_struct = None
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self.has_output_struct = None
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self._indent_level = 0
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def get_package_declaration(self) -> str:
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"""
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If this hwif requires a package, generate the string
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"""
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lines = []
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lines.append(f"package {self.package_name};")
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self._indent_level += 1
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self.has_input_struct = self._do_struct_addressable(lines, self.top_node, is_input=True)
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self.has_output_struct = self._do_struct_addressable(lines, self.top_node, is_input=False)
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self._indent_level -= 1
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lines.append("")
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lines.append("endpackage")
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return "\n".join(lines)
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@property
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def port_declaration(self) -> str:
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"""
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Returns the declaration string for all I/O ports in the hwif group
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"""
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# Assume get_package_declaration() is always called prior to this
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assert self.has_input_struct is not None
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assert self.has_output_struct is not None
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lines = []
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if self.has_input_struct:
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lines.append(f"input {self.package_name}::{self._get_struct_name(self.top_node, is_input=True)} hwif_in")
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if self.has_output_struct:
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lines.append(f"output {self.package_name}::{self._get_struct_name(self.top_node, is_input=False)} hwif_out")
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return ",\n".join(lines)
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#---------------------------------------------------------------------------
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# Struct generation functions
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#---------------------------------------------------------------------------
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@property
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def _indent(self) -> str:
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return " " * self._indent_level
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def _get_node_array_suffix(self, node:AddressableNode) -> str:
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if node.is_array:
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return "".join([f'[{dim}]' for dim in node.array_dimensions])
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return ""
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def _get_struct_name(self, node:Node, is_input:bool = True) -> str:
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base = node.get_rel_path(
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self.top_node.parent,
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hier_separator="__",
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array_suffix="x",
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empty_array_suffix="x"
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)
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if is_input:
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return f'{base}_in_t'
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return f'{base}__out_t'
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def _do_struct_addressable(self, lines:list, node:AddressableNode, is_input:bool = True) -> bool:
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struct_children = []
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# Generate structs for children first
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for child in node.children():
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if isinstance(child, AddressableNode):
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if self._do_struct_addressable(lines, child, is_input):
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struct_children.append(child)
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elif isinstance(child, FieldNode):
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if self._do_struct_field(lines, child, is_input):
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struct_children.append(child)
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elif is_input and isinstance(child, SignalNode):
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# No child struct needed here
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# TODO: Skip if this is a top-level child
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struct_children.append(child)
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# Generate this addressable node's struct
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if struct_children:
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lines.append("")
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lines.append(f"{self._indent}// {node.get_rel_path(self.top_node.parent)}")
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lines.append(f"{self._indent}typedef struct {{")
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self._indent_level += 1
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for child in struct_children:
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if isinstance(child, AddressableNode):
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lines.append(f"{self._indent}{self._get_struct_name(child, is_input)} {child.inst_name}{self._get_node_array_suffix(child)};")
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elif isinstance(child, FieldNode):
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lines.append(f"{self._indent}{self._get_struct_name(child, is_input)} {child.inst_name};")
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elif isinstance(child, SignalNode):
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if child.width == 1:
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lines.append(f"{self._indent}logic {child.inst_name};")
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else:
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lines.append(f"{self._indent}logic [{child.msb}:{child.lsb}] {child.inst_name};")
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self._indent_level -= 1
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lines.append(f"{self._indent}}} {self._get_struct_name(node, is_input)};")
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return bool(struct_children)
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def _do_struct_field(self, lines:list, node:FieldNode, is_input:bool = True) -> bool:
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contents = []
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if is_input:
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contents = self._get_struct_input_field_contents(node)
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else:
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contents = self._get_struct_output_field_contents(node)
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if contents:
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lines.append("")
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lines.append(f"{self._indent}// {node.get_rel_path(self.top_node.parent)}")
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lines.append(f"{self._indent}typedef struct {{")
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self._indent_level += 1
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for member in contents:
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lines.append(self._indent + member)
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self._indent_level -= 1
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lines.append(f"{self._indent}}} {self._get_struct_name(node, is_input)};")
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return bool(contents)
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def _get_struct_input_field_contents(self, node:FieldNode) -> List[str]:
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contents = []
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# Provide input to field's value if it is writable by hw
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if self.has_value_input(node):
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if node.width == 1:
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contents.append("logic value;")
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else:
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contents.append(f"logic [{node.width-1}:0] value;")
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# TODO:
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"""
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we/wel
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if either is boolean, and true
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not part of external hwif if reference
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mutually exclusive
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hwclr/hwset
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if either is boolean, and true
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not part of external hwif if reference
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incr/decr
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if counter=true, generate BOTH
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incrvalue/decrvalue
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if either incrwidth/decrwidth are set
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signals!
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any signal instances instantiated in the scope
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"""
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return contents
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def _get_struct_output_field_contents(self, node:FieldNode) -> List[str]:
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contents = []
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# Expose field's value if it is readable by hw
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if self.has_value_output(node):
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if node.width == 1:
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contents.append("logic value;")
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else:
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contents.append(f"logic [{node.width-1}:0] value;")
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# TODO:
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"""
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bitwise reductions
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if anded, ored, xored == True, output a signal
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swmod/swacc
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event strobes
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Are there was_written/was_read strobes too?
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"""
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return contents
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#---------------------------------------------------------------------------
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# hwif utility functions
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#---------------------------------------------------------------------------
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def has_value_input(self, obj: Union[FieldNode, SignalNode]) -> bool:
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"""
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Returns True if the object infers an input wire in the hwif
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"""
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if isinstance(obj, FieldNode):
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return obj.is_hw_writable
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elif isinstance(obj, SignalNode):
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# Signals are implicitly always inputs
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return True
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else:
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raise RuntimeError
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def has_value_output(self, obj: FieldNode) -> bool:
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"""
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Returns True if the object infers an output wire in the hwif
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"""
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# TODO: Extend this for signals and prop references?
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return obj.is_hw_readable
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def get_input_identifier(self, obj: Union[FieldNode, SignalNode, PropertyReference]) -> str:
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"""
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Returns the identifier string that best represents the input object.
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if obj is:
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Field: the fields input value port
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Signal: signal input value
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Prop reference:
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could be an implied hwclr/hwset/swwe/swwel/we/wel input
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Raise a runtime error if an illegal prop ref is requested, or if
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the prop ref is not actually implied, but explicitly ref a component
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TODO: finish this
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raises an exception if obj is invalid
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"""
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raise NotImplementedError()
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def get_output_identifier(self, obj: FieldNode) -> str:
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"""
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Returns the identifier string that best represents the output object.
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if obj is:
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Field: the fields output value port
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Property ref: this is also part of the struct
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TODO: finish this
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raises an exception if obj is invalid
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"""
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raise NotImplementedError()
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