diff --git a/docs/cpuif/apb3.rst b/docs/cpuif/apb.rst
similarity index 52%
rename from docs/cpuif/apb3.rst
rename to docs/cpuif/apb.rst
index e1647dc..bd11b91 100644
--- a/docs/cpuif/apb3.rst
+++ b/docs/cpuif/apb.rst
@@ -1,5 +1,24 @@
-AMBA 3 APB
-==========
+AMBA APB
+========
+
+Both APB3 and APB4 standards are supported.
+
+.. warning::
+    Some IP vendors will incorrectly implement the address signalling
+    assuming word-addresses. (that each increment of ``PADDR`` is the next word)
+
+    For this exporter, values on the interface's ``PADDR`` input are interpreted
+    as byte-addresses. (an APB interface with 32-bit wide data increments
+    ``PADDR`` in steps of 4 for every word). Even though APB protocol does not
+    allow for unaligned transfers, this is in accordance to the official AMBA
+    specification.
+
+    Be sure to double-check the interpretation of your interconnect IP. A simple
+    bit-shift operation can be used to correct this if necessary.
+
+
+APB3
+----
 
 Implements the register block using an
 `AMBA 3 APB <https://developer.arm.com/documentation/ihi0024/b/Introduction/About-the-AMBA-3-APB>`_
@@ -18,14 +37,21 @@ Flattened inputs/outputs
     Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened`
 
 
-.. warning::
-    Some IP vendors will incorrectly implement the address signalling
-    assuming word-addresses. (that each increment of ``PADDR`` is the next word)
+APB4
+----
 
-    For this exporter, values on the interface's ``PADDR`` input are interpreted
-    as byte-addresses. (a 32-bit APB bus increments ``PADDR`` in steps of 4)
-    Although APB protocol does not allow for unaligned transfers, this is in
-    accordance to the official AMBA bus specification.
+Implements the register block using an
+`AMBA 4 APB <https://developer.arm.com/documentation/ihi0024/d/?lang=en>`_
+CPU interface.
 
-    Be sure to double-check the interpretation of your interconnect IP. A simple
-    bit-shift operation can be used to correct this if necessary.
+The APB4 CPU interface comes in two i/o port flavors:
+
+SystemVerilog Interface
+    Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
+
+    Interface Definition: :download:`apb4_intf.sv <../../tests/lib/cpuifs/apb4/apb4_intf.sv>`
+
+Flattened inputs/outputs
+    Flattens the interface into discrete input and output ports.
+
+    Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened`
diff --git a/docs/index.rst b/docs/index.rst
index dfbbef3..e519168 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -94,8 +94,7 @@ Links
     :caption: CPU Interfaces
 
     cpuif/introduction
-    cpuif/apb3
-    cpuif/apb4
+    cpuif/apb
     cpuif/axi4lite
     cpuif/passthrough
     cpuif/internal_protocol