From ec78f2b199f6cf42aeea27576f1981bc85523547 Mon Sep 17 00:00:00 2001
From: Alex Mykyta <amykyta3@users.noreply.github.com>
Date: Tue, 13 Sep 2022 22:44:30 -0700
Subject: [PATCH] Clean up cpuif data_width_bytes usage

---
 src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv    | 2 +-
 src/peakrdl_regblock/cpuif/apb4/__init__.py     | 4 ----
 src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv    | 2 +-
 src/peakrdl_regblock/cpuif/axi4lite/__init__.py | 6 +-----
 src/peakrdl_regblock/cpuif/base.py              | 4 ++++
 5 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv b/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
index bf28783..e51198d 100644
--- a/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
@@ -16,7 +16,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                 {%- if cpuif.data_width == 8 %}
                 cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                 {%- else %}
-                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width//8)}}], {{clog2(cpuif.data_width//8)}}'b0};
+                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
                 {%- endif %}
                 cpuif_wr_data <= {{cpuif.signal("pwdata")}};
             end
diff --git a/src/peakrdl_regblock/cpuif/apb4/__init__.py b/src/peakrdl_regblock/cpuif/apb4/__init__.py
index b244dd4..a74ae49 100644
--- a/src/peakrdl_regblock/cpuif/apb4/__init__.py
+++ b/src/peakrdl_regblock/cpuif/apb4/__init__.py
@@ -10,10 +10,6 @@ class APB4_Cpuif(CpuifBase):
     def signal(self, name:str) -> str:
         return "s_apb." + name.upper()
 
-    @property
-    def data_width_bytes(self) -> int:
-        return self.data_width // 8
-
 
 class APB4_Cpuif_flattened(APB4_Cpuif):
     @property
diff --git a/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv b/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
index 97cf5e8..bdc5c44 100644
--- a/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
@@ -17,7 +17,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                 {%- if cpuif.data_width == 8 %}
                 cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                 {%- else %}
-                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width//8)}}], {{clog2(cpuif.data_width//8)}}'b0};
+                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
                 {%- endif %}
                 cpuif_wr_data <= {{cpuif.signal("pwdata")}};
                 for(int i=0; i<{{cpuif.data_width_bytes}}; i++) begin
diff --git a/src/peakrdl_regblock/cpuif/axi4lite/__init__.py b/src/peakrdl_regblock/cpuif/axi4lite/__init__.py
index 222aa9f..60553f6 100644
--- a/src/peakrdl_regblock/cpuif/axi4lite/__init__.py
+++ b/src/peakrdl_regblock/cpuif/axi4lite/__init__.py
@@ -10,10 +10,6 @@ class AXI4Lite_Cpuif(CpuifBase):
     def signal(self, name:str) -> str:
         return "s_axil." + name.upper()
 
-    @property
-    def data_width_bytes(self) -> int:
-        return self.data_width // 8
-
     @property
     def regblock_latency(self) -> int:
         return max(self.exp.min_read_latency, self.exp.min_write_latency)
@@ -49,7 +45,7 @@ class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
             "output logic " + self.signal("wready"),
             "input wire " + self.signal("wvalid"),
             f"input wire [{self.data_width-1}:0] " + self.signal("wdata"),
-            f"input wire [{self.data_width//8-1}:0]" + self.signal("wstrb"),
+            f"input wire [{self.data_width_bytes-1}:0]" + self.signal("wstrb"),
 
             "input wire " + self.signal("bready"),
             "output logic " + self.signal("bvalid"),
diff --git a/src/peakrdl_regblock/cpuif/base.py b/src/peakrdl_regblock/cpuif/base.py
index 654ca5c..2d63a86 100644
--- a/src/peakrdl_regblock/cpuif/base.py
+++ b/src/peakrdl_regblock/cpuif/base.py
@@ -21,6 +21,10 @@ class CpuifBase:
         self.data_width = data_width
         self.addr_width = addr_width
 
+    @property
+    def data_width_bytes(self) -> int:
+        return self.data_width // 8
+
     @property
     def port_declaration(self) -> str:
         raise NotImplementedError()