bslathi19/PeakRDL-regblock
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This commit is contained in:
Alex Mykyta
2021-12-12 17:10:32 -08:00
parent 3dee090467
commit ee8d74b455
37 changed files with 32 additions and 114 deletions
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1
peakrdl/regblock/cpuif/apb3/apb3_tmpl.sv
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@@ -31,7 +31,6 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
end
end
end
assign cpuif_wr_biten = '1;
// Response
assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;

3
peakrdl/regblock/module_tmpl.sv
View File

@@ -26,7 +26,6 @@ module {{module_name}} (
logic cpuif_req_is_wr;
logic [{{cpuif.addr_width-1}}:0] cpuif_addr;
logic [{{cpuif.data_width-1}}:0] cpuif_wr_data;
logic [{{cpuif.data_width-1}}:0] cpuif_wr_biten;
logic cpuif_rd_ack;
logic [{{cpuif.data_width-1}}:0] cpuif_rd_data;
@@ -45,7 +44,6 @@ module {{module_name}} (
logic decoded_req;
logic decoded_req_is_wr;
logic [{{cpuif.data_width-1}}:0] decoded_wr_data;
logic [{{cpuif.data_width-1}}:0] decoded_wr_biten;
always_comb begin
{{address_decode.get_implementation()|indent(8)}}
@@ -59,7 +57,6 @@ module {{module_name}} (
assign decoded_req = cpuif_req;
assign decoded_req_is_wr = cpuif_req_is_wr;
assign decoded_wr_data = cpuif_wr_data;
assign decoded_wr_biten = cpuif_wr_biten;
//--------------------------------------------------------------------------
// Field logic