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This commit is contained in:
Alex Mykyta
2023-08-03 22:53:22 -07:00
parent 5c3dd6e6bb
commit eef8f7cdb4
13 changed files with 118 additions and 92 deletions
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18
docs/cpuif/apb.rst
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@@ -27,14 +27,15 @@ CPU interface.
The APB3 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif`
Interface Definition: :download:`apb3_intf.sv <../../hdl-src/apb3_intf.sv>`
* Command line: ``--cpuif apb3``
* Interface Definition: :download:`apb3_intf.sv <../../hdl-src/apb3_intf.sv>`
* Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened`
* Command line: ``--cpuif apb3-flat``
* Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened`
APB4
@@ -47,11 +48,12 @@ CPU interface.
The APB4 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
Interface Definition: :download:`apb4_intf.sv <../../hdl-src/apb4_intf.sv>`
* Command line: ``--cpuif apb4``
* Interface Definition: :download:`apb4_intf.sv <../../hdl-src/apb4_intf.sv>`
* Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened`
* Command line: ``--cpuif apb4-flat``
* Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened`

9
docs/cpuif/avalon.rst
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@@ -8,14 +8,15 @@ CPU interface.
The Avalon interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif`
Interface Definition: :download:`avalon_mm_intf.sv <../../hdl-src/avalon_mm_intf.sv>`
* Command line: ``--cpuif avalon-mm``
* Interface Definition: :download:`avalon_mm_intf.sv <../../hdl-src/avalon_mm_intf.sv>`
* Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif_flattened`
* Command line: ``--cpuif avalon-mm-flat``
* Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif_flattened`
Implementation Details

9
docs/cpuif/axi4lite.rst
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@@ -10,14 +10,15 @@ CPU interface.
The AXI4-Lite CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`
* Command line: ``--cpuif axi4-lite``
* Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`
* Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
* Command line: ``--cpuif axi4-lite-flat``
* Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
Pipelined Performance

27
docs/cpuif/customizing.rst
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@@ -65,7 +65,8 @@ you can define your own.
in this shall implement a translation between your custom protocol and the
:ref:`cpuif_protocol`.
Reminder that this template will be preprocessed using Jinja, so you can use
Reminder that this template will be preprocessed using
`Jinja <https://jinja.palletsprojects.com>`_, so you can use
some templating tags to dynamically render content. See the implementations of
existing CPU interfaces as an example.
@@ -75,16 +76,26 @@ you can define your own.
Define the port declaration string, and provide a reference to your template file.
3. Use your new CPUIF definition when exporting.
4. If you think the CPUIF protocol is something others might find useful, let me know and I can add it to PeakRDL!
4. If you think the CPUIF protocol is something others might find useful, let me
know and I can add it to PeakRDL!
Entry point for the PeakRDL command line tool
---------------------------------------------
To make your custom CPUIF class visible to the `PeakRDL command-line tool <https://peakrdl.readthedocs.io>`_,
provide an entry point linkage in your package's ``setup.py``. This advertises
your custom CPUIF class to the PeakRDL-regblock tool as a plugin that should be
loaded, and made available as a command-line option in PeakRDL.
Loading into the PeakRDL command line tool
------------------------------------------
There are two ways to make your custom CPUIF class visible to the
`PeakRDL command-line tool <https://peakrdl.readthedocs.io>`_.
Via the PeakRDL TOML
^^^^^^^^^^^^^^^^^^^^
The easiest way to add your cpuif is via the TOML config file. See the
:ref:`peakrdl_cfg` section for more details.
Via a package's entry point definition
--------------------------------------
If you are publishing a collecxtion of PeakRDL plugins as an installable Python
package, you can advertise them to PeakRDL using an entry point.
This advertises your custom CPUIF class to the PeakRDL-regblock tool as a plugin
that should be loaded, and made available as a command-line option in PeakRDL.
.. code-block:: python
:emphasize-lines: 7-11

3
docs/cpuif/passthrough.rst
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@@ -4,6 +4,7 @@ CPUIF Passthrough
This CPUIF mode bypasses the protocol converter stage and directly exposes the
internal CPUIF handshake signals to the user.
Class: :class:`peakrdl_regblock.cpuif.passthrough.PassthroughCpuif`
* Command line: ``--cpuif passthrough``
* Class: :class:`peakrdl_regblock.cpuif.passthrough.PassthroughCpuif`
For more details on the protocol itself, see: :ref:`cpuif_protocol`.