Doc updates

docs/index.rst

@@ -31,59 +31,19 @@ Install from `PyPi`_ using pip
 
 
 
-Quick Start - PeakRDL
----------------------
+Example
+-------
 The easiest way is to use the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
 
 .. code-block:: bash
 
+    # Install the command line tool
+    python3 -m pip install peakrdl
+
+    # Export!
     peakrdl regblock atxmega_spi.rdl -o regblock/ --cpuif axi4-lite
 
 
-Quick Start - API
------------------
-Otherwise if you want, there is a Python API.
-Below is a simple example that demonstrates how to generate a SystemVerilog
-implementation from SystemRDL source.
-
-.. code-block:: python
-    :emphasize-lines: 2-4, 29-33
-
-    from systemrdl import RDLCompiler, RDLCompileError
-    from peakrdl_regblock import RegblockExporter
-    from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif
-    from peakrdl_regblock.udps import ALL_UDPS
-
-    input_files = [
-        "PATH/TO/my_register_block.rdl"
-    ]
-
-    # Create an instance of the compiler
-    rdlc = RDLCompiler()
-
-    # Register all UDPs that 'regblock' requires
-    for udp in ALL_UDPS:
-        rdlc.register_udp(udp)
-
-    try:
-        # Compile your RDL files
-        for input_file in input_files:
-            rdlc.compile_file(input_file)
-
-        # Elaborate the design
-        root = rdlc.elaborate()
-    except RDLCompileError:
-        # A compilation error occurred. Exit with error code
-        sys.exit(1)
-
-    # Export a SystemVerilog implementation
-    exporter = RegblockExporter()
-    exporter.export(
-        root, "path/to/output_dir",
-        cpuif_cls=AXI4Lite_Cpuif
-    )
-
-
 Links
 -----
 
@@ -101,9 +61,9 @@ Links
     architecture
     hwif
     configuring
-    api
     limitations
     licensing
+    api
 
 .. toctree::
     :hidden: