fill in more hwif utility functions for dereferencer
This commit is contained in:
Alex Mykyta
@@ -1,105 +1,77 @@
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import re
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from typing import TYPE_CHECKING, List
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from typing import TYPE_CHECKING
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from systemrdl.node import AddrmapNode, FieldNode
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from systemrdl.rdltypes import PropertyReference
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from ..utils import get_indexed_path
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from .field_builder import FieldBuilder, FieldStorageStructGenerator
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from .field_builder import CombinationalStructGenerator, FieldLogicGenerator
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from systemrdl.node import Node, AddressableNode, RegNode, FieldNode
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if TYPE_CHECKING:
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from ..exporter import RegblockExporter
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class FieldLogic:
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def __init__(self, exporter:'RegblockExporter', top_node:Node):
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def __init__(self, exporter:'RegblockExporter'):
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self.exporter = exporter
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self.top_node = top_node
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self.field_builder = FieldBuilder(exporter)
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self._indent_level = 0
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@property
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def top_node(self) -> AddrmapNode:
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return self.exporter.top_node
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def get_storage_struct(self) -> str:
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lines = []
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self._do_struct(lines, self.top_node, is_top=True)
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struct_gen = FieldStorageStructGenerator()
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s = struct_gen.get_struct(self.top_node, "field_storage_t")
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# Only declare the storage struct if it exists
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if lines:
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lines.append(f"{self._indent}field_storage_t field_storage;")
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return "\n".join(lines)
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if s is None:
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return ""
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return s + "\nfield_storage_t field_storage;"
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def get_combo_struct(self) -> str:
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struct_gen = CombinationalStructGenerator(self.field_builder)
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s = struct_gen.get_struct(self.top_node, "field_combo_t")
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# Only declare the storage struct if it exists
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if s is None:
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return ""
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return s + "\nfield_combo_t field_combo;"
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def get_implementation(self) -> str:
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return "TODO:"
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gen = FieldLogicGenerator(self.field_builder)
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s = gen.get_content(self.top_node)
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if s is None:
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return ""
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return s
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#---------------------------------------------------------------------------
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# Field utility functions
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#---------------------------------------------------------------------------
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def get_storage_identifier(self, node: FieldNode):
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def get_storage_identifier(self, node: FieldNode) -> str:
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"""
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Returns the Verilog string that represents the storage register element
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for the referenced field
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"""
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assert node.implements_storage
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path = node.get_rel_path(self.top_node, empty_array_suffix="[!]")
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# replace unknown indexes with incrementing iterators i0, i1, ...
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class repl:
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def __init__(self):
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self.i = 0
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def __call__(self, match):
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s = f'i{self.i}'
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self.i += 1
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return s
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path = re.sub(r'!', repl(), path)
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path = get_indexed_path(self.top_node, node)
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return "field_storage." + path
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def get_field_next_identifier(self, node: FieldNode) -> str:
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"""
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Returns a Verilog string that represents the field's next-state.
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This is specifically for use in Field->next property references.
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"""
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# TODO: Implement this
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raise NotImplementedError
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#---------------------------------------------------------------------------
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# Struct generation functions
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#---------------------------------------------------------------------------
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@property
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def _indent(self) -> str:
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return " " * self._indent_level
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def _get_node_array_suffix(self, node:AddressableNode) -> str:
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if node.is_array:
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return "".join([f'[{dim}]' for dim in node.array_dimensions])
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return ""
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def _do_struct(self, lines:List[str], node:AddressableNode, is_top:bool = False) -> bool:
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# Collect struct members first
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contents = []
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self._indent_level += 1
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for child in node.children():
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if isinstance(child, RegNode):
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self._do_reg_struct(contents, child)
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elif isinstance(child, AddressableNode):
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self._do_struct(contents, child)
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self._indent_level -= 1
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# If struct is not empty, emit a struct!
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if contents:
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if is_top:
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lines.append(f"{self._indent}typedef struct {{")
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else:
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lines.append(f"{self._indent}struct {{")
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lines.extend(contents)
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if is_top:
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lines.append(f"{self._indent}}} field_storage_t;")
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else:
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lines.append(f"{self._indent}}} {node.inst_name}{self._get_node_array_suffix(node)};")
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def _do_reg_struct(self, lines:List[str], node:RegNode) -> None:
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fields = []
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for field in node.fields():
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if field.implements_storage:
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fields.append(field)
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if not fields:
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return
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lines.append(f"{self._indent}struct {{")
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self._indent_level += 1
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for field in fields:
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if field.width == 1:
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lines.append(f"{self._indent}logic {field.inst_name};")
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else:
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lines.append(f"{self._indent}logic [{field.width-1}:0] {field.inst_name};")
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self._indent_level -= 1
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lines.append(f"{self._indent}}} {node.inst_name}{self._get_node_array_suffix(node)};")
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def get_counter_control_identifier(self, prop_ref: PropertyReference) -> str:
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"""
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Return the Veriog string that represents the field's inferred incr/decr strobe signal.
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prop_ref will be either an incr or decr property reference, and it is already known that
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the incr/decr properties are not explicitly set by the user and are therefore inferred.
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"""
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# TODO: Implement this
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raise NotImplementedError
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95
peakrdl/regblock/field_logic/bases.py
Normal file
95
peakrdl/regblock/field_logic/bases.py
Normal file
@@ -0,0 +1,95 @@
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from typing import TYPE_CHECKING, List
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import enum
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from ..utils import get_indexed_path
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if TYPE_CHECKING:
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from systemrdl.node import FieldNode
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from ..exporter import RegblockExporter
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class AssignmentPrecedence(enum.IntEnum):
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"""
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Enumeration of standard assignment precedence groups.
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Each value represents the precedence of a single conditional assignment
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category that determines a field's next state.
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Higher value denotes higher precedence
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Important: If inserting custom intermediate assignment rules, do not rely on the absolute
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value of the enumeration. Insert your rules relative to an existing precedence:
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FieldBuilder.add_hw_conditional(MyConditional, HW_WE + 1)
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"""
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# Software access assignment groups
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SW_ONREAD = 5000
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SW_ONWRITE = 4000
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# Hardware access assignment groups
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HW_WE = 3000
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HWSET = 2000
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HWCLR = 1000
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COUNTER_INCR_DECR = 0
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class SVLogic:
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"""
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Represents a SystemVerilog logic signal
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"""
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def __init__(self, name: str, width: int, default_assignment: str) -> None:
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self.name = name
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self.width = width
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self.default_assignment = default_assignment
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def __eq__(self, o: object) -> bool:
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if not isinstance(o, SVLogic):
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return False
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return (
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o.name == self.name
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and o.width == self.width
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and o.default_assignment == self.default_assignment
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)
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class NextStateConditional:
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"""
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Decribes a single conditional action that determines the next state of a field
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Provides information to generate the following content:
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if(<conditional>) begin
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<assignments>
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end
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"""
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def __init__(self, exporter:'RegblockExporter'):
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self.exporter = exporter
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def is_match(self, field: 'FieldNode') -> bool:
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"""
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Returns True if this conditional is relevant to the field. If so,
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it instructs the FieldBuider that Verilog for this conditional shall
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be emitted
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"""
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raise NotImplementedError
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def get_field_path(self, field:'FieldNode') -> str:
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return get_indexed_path(self.exporter.top_node, field)
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def get_conditional(self, field: 'FieldNode') -> str:
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"""
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Returns the rendered conditional text
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"""
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raise NotImplementedError
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def get_assignments(self, field: 'FieldNode') -> List[str]:
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"""
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Returns a list of rendered assignment strings
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This will basically always be two:
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<field>.next = <next value>
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<field>.load_next = '1;
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"""
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def get_extra_combo_signals(self, field: 'FieldNode') -> List[SVLogic]:
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return []
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176
peakrdl/regblock/field_logic/field_builder.py
Normal file
176
peakrdl/regblock/field_logic/field_builder.py
Normal file
@@ -0,0 +1,176 @@
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from typing import TYPE_CHECKING
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from collections import OrderedDict
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from systemrdl.rdltypes import PrecedenceType
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from .bases import AssignmentPrecedence, NextStateConditional
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from . import sw_onread
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from . import sw_onwrite
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from ..struct_generator import RDLStructGenerator
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from ..forloop_generator import RDLForLoopGenerator
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from ..utils import get_indexed_path, get_always_ff_event
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from ..signals import RDLSignal
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if TYPE_CHECKING:
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from typing import Dict, List
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from systemrdl.node import FieldNode, AddrmapNode
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from ..exporter import RegblockExporter
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class FieldBuilder:
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def __init__(self, exporter:'RegblockExporter'):
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self.exporter = exporter
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self._hw_conditionals = {} # type: Dict[int, List[NextStateConditional]]
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self._sw_conditionals = {} # type: Dict[int, List[NextStateConditional]]
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self.init_conditionals()
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@property
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def top_node(self) -> 'AddrmapNode':
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return self.exporter.top_node
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def add_hw_conditional(self, conditional: NextStateConditional, precedence: AssignmentPrecedence) -> None:
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# TODO: Add docstring!
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if precedence not in self._hw_conditionals:
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self._hw_conditionals[precedence] = []
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self._hw_conditionals[precedence].append(conditional)
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def add_sw_conditional(self, conditional: NextStateConditional, precedence: AssignmentPrecedence) -> None:
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# TODO: Add docstring!
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if precedence not in self._sw_conditionals:
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self._sw_conditionals[precedence] = []
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self._sw_conditionals[precedence].append(conditional)
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def init_conditionals(self) -> None:
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# TODO: Add docstring!
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# TODO: Add all the other things
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self.add_sw_conditional(sw_onread.ClearOnRead(self.exporter), AssignmentPrecedence.SW_ONREAD)
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self.add_sw_conditional(sw_onread.SetOnRead(self.exporter), AssignmentPrecedence.SW_ONREAD)
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self.add_hw_conditional(sw_onwrite.WriteOneSet(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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self.add_hw_conditional(sw_onwrite.WriteOneClear(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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self.add_hw_conditional(sw_onwrite.WriteOneToggle(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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self.add_hw_conditional(sw_onwrite.WriteZeroSet(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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self.add_hw_conditional(sw_onwrite.WriteZeroClear(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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self.add_hw_conditional(sw_onwrite.WriteZeroToggle(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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self.add_hw_conditional(sw_onwrite.WriteClear(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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self.add_hw_conditional(sw_onwrite.WriteSet(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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self.add_hw_conditional(sw_onwrite.Write(self.exporter), AssignmentPrecedence.SW_ONWRITE)
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def _get_X_conditionals(self, conditionals: 'Dict[int, List[NextStateConditional]]', field: 'FieldNode') -> 'List[NextStateConditional]':
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result = []
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precedences = sorted(conditionals.keys(), reverse=True)
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for precedence in precedences:
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for conditional in conditionals[precedence]:
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if conditional.is_match(field):
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result.append(conditional)
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return result
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def get_conditionals(self, field: 'FieldNode') -> 'List[NextStateConditional]':
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# TODO: Add docstring! - list of NextStateConditional. Highest precedence comes first
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sw_precedence = (field.get_property('precedence') == PrecedenceType.sw)
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result = []
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if sw_precedence:
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result.extend(self._get_X_conditionals(self._sw_conditionals, field))
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result.extend(self._get_X_conditionals(self._hw_conditionals, field))
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if not sw_precedence:
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result.extend(self._get_X_conditionals(self._sw_conditionals, field))
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return result
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class CombinationalStructGenerator(RDLStructGenerator):
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def __init__(self, field_builder: FieldBuilder):
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super().__init__()
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self.field_builder = field_builder
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def enter_Field(self, node: 'FieldNode') -> None:
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# If a field doesn't implement storage, it is not relevant here
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if not node.implements_storage:
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return
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# collect any extra combo signals that this field requires
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extra_combo_signals = OrderedDict()
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for conditional in self.field_builder.get_conditionals(node):
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for signal in conditional.get_extra_combo_signals(node):
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if signal.name in extra_combo_signals:
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# Assert that subsequent declarations of the same signal
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# are identical
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assert signal == extra_combo_signals[signal.name]
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else:
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extra_combo_signals[signal.name] = signal
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self.push_struct(node.inst_name)
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self.add_member("next", node.width)
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self.add_member("load_next")
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for signal in extra_combo_signals.values():
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self.add_member(signal.name, signal.width)
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self.pop_struct()
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class FieldStorageStructGenerator(RDLStructGenerator):
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def enter_Field(self, node: 'FieldNode') -> None:
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if node.implements_storage:
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self.add_member(node.inst_name, node.width)
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class FieldLogicGenerator(RDLForLoopGenerator):
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i_type = "genvar"
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def __init__(self, field_builder: FieldBuilder):
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super().__init__()
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self.field_builder = field_builder
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self.template = self.field_builder.exporter.jj_env.get_template(
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"field_logic/templates/field_storage.sv"
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)
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def enter_Field(self, node: 'FieldNode') -> None:
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# If a field doesn't implement storage, it is not relevant here
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if not node.implements_storage:
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return
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conditionals = self.field_builder.get_conditionals(node)
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extra_combo_signals = OrderedDict()
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for conditional in conditionals:
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for signal in conditional.get_extra_combo_signals(node):
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extra_combo_signals[signal.name] = signal
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reset_value = node.get_property("reset") or 0
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sig = node.get_property("resetsignal")
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if sig is not None:
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resetsignal = RDLSignal(sig)
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else:
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resetsignal = self.field_builder.exporter.default_resetsignal
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context = {
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'node': node,
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'reset': self.field_builder.exporter.dereferencer.get_value(reset_value),
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'field_path': get_indexed_path(self.field_builder.top_node, node),
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'extra_combo_signals': extra_combo_signals,
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'conditionals': conditionals,
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'resetsignal': resetsignal,
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'get_always_ff_event': get_always_ff_event,
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'has_value_output': self.field_builder.exporter.hwif.has_value_output,
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'get_output_identifier': self.field_builder.exporter.hwif.get_output_identifier,
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}
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self.add_content(self.template.render(context))
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38
peakrdl/regblock/field_logic/sw_onread.py
Normal file
38
peakrdl/regblock/field_logic/sw_onread.py
Normal file
@@ -0,0 +1,38 @@
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from typing import TYPE_CHECKING, List
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from systemrdl.rdltypes import OnReadType
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from .bases import NextStateConditional
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if TYPE_CHECKING:
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from systemrdl.node import FieldNode
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class _OnRead(NextStateConditional):
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onreadtype = None
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def is_match(self, field: 'FieldNode') -> bool:
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return field.get_property("onread") == self.onreadtype
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def get_conditional(self, field: 'FieldNode') -> str:
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strb = self.exporter.dereferencer.get_access_strobe(field)
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return f"decoded_req && !decoded_req_is_wr && {strb}"
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class ClearOnRead(_OnRead):
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onreadtype = OnReadType.rclr
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def get_assignments(self, field: 'FieldNode') -> List[str]:
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field_path = self.get_field_path(field)
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return [
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f"field_combo.{field_path}.next = '0;",
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f"field_combo.{field_path}.load_next = '1;",
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]
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||||
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||||
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class SetOnRead(_OnRead):
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onreadtype = OnReadType.rset
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||||
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||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
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||||
field_path = self.get_field_path(field)
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||||
return [
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||||
f"field_combo.{field_path}.next = '1;",
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||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
107
peakrdl/regblock/field_logic/sw_onwrite.py
Normal file
107
peakrdl/regblock/field_logic/sw_onwrite.py
Normal file
@@ -0,0 +1,107 @@
|
||||
from typing import TYPE_CHECKING, List
|
||||
|
||||
from systemrdl.rdltypes import OnWriteType
|
||||
|
||||
from .bases import NextStateConditional
|
||||
|
||||
if TYPE_CHECKING:
|
||||
from systemrdl.node import FieldNode
|
||||
|
||||
class _OnWrite(NextStateConditional):
|
||||
onwritetype = None
|
||||
def is_match(self, field: 'FieldNode') -> bool:
|
||||
return field.get_property("onwrite") == self.onwritetype
|
||||
|
||||
def get_conditional(self, field: 'FieldNode') -> str:
|
||||
strb = self.exporter.dereferencer.get_access_strobe(field)
|
||||
return f"decoded_req && decoded_req_is_wr && {strb}"
|
||||
|
||||
class WriteOneSet(_OnWrite):
|
||||
onwritetype = OnWriteType.woset
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = field_storage.{field_path} | decoded_wr_data;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
|
||||
class WriteOneClear(_OnWrite):
|
||||
onwritetype = OnWriteType.woclr
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = field_storage.{field_path} & ~decoded_wr_data;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
|
||||
class WriteOneToggle(_OnWrite):
|
||||
onwritetype = OnWriteType.wot
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = field_storage.{field_path} ^ decoded_wr_data;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
|
||||
class WriteZeroSet(_OnWrite):
|
||||
onwritetype = OnWriteType.wzs
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = field_storage.{field_path} | ~decoded_wr_data;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
|
||||
class WriteZeroClear(_OnWrite):
|
||||
onwritetype = OnWriteType.wzc
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = field_storage.{field_path} & decoded_wr_data;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
|
||||
class WriteZeroToggle(_OnWrite):
|
||||
onwritetype = OnWriteType.wzt
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = field_storage.{field_path} ^ ~decoded_wr_data;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
|
||||
class WriteClear(_OnWrite):
|
||||
onwritetype = OnWriteType.wclr
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = '0;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
|
||||
class WriteSet(_OnWrite):
|
||||
onwritetype = OnWriteType.wset
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = '1;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
|
||||
class Write(_OnWrite):
|
||||
onwritetype = None
|
||||
|
||||
def get_assignments(self, field: 'FieldNode') -> List[str]:
|
||||
field_path = self.get_field_path(field)
|
||||
return [
|
||||
f"field_combo.{field_path}.next = decoded_wr_data;",
|
||||
f"field_combo.{field_path}.load_next = '1;",
|
||||
]
|
||||
25
peakrdl/regblock/field_logic/templates/field_storage.sv
Normal file
25
peakrdl/regblock/field_logic/templates/field_storage.sv
Normal file
@@ -0,0 +1,25 @@
|
||||
// Field: {{node.get_path()}}
|
||||
always_comb begin
|
||||
field_combo.{{field_path}}.next = '0;
|
||||
field_combo.{{field_path}}.load_next = '0;
|
||||
{%- for signal in extra_combo_signals %}
|
||||
field_combo.{{field_path}}.{{signal.name}} = {{signal.default_assignment}};
|
||||
{%- endfor %}
|
||||
{%- for conditional in conditionals %}
|
||||
{% if not loop.first %}end else {% endif %}if({{conditional.get_conditional(node)}}) begin
|
||||
{%- for assignment in conditional.get_assignments(node) %}
|
||||
{{assignment|indent}}
|
||||
{%- endfor %}
|
||||
end
|
||||
{%- endfor %}
|
||||
end
|
||||
always_ff {{get_always_ff_event(resetsignal)}} begin
|
||||
if({{resetsignal.activehigh_identifier}}) begin
|
||||
field_storage.{{field_path}} <= {{reset}};
|
||||
end else if(field_combo.{{field_path}}.load_next) begin
|
||||
field_storage.{{field_path}} <= field_combo.{{field_path}}.next;
|
||||
end
|
||||
end
|
||||
{% if has_value_output(node) -%}
|
||||
assign {{get_output_identifier(node)}} = field_storage.{{field_path}};
|
||||
{%- endif -%}
|
||||
Reference in New Issue
Block a user