Add singlepulse support
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@@ -5,6 +5,7 @@ from systemrdl.rdltypes import PropertyReference, PrecedenceType
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from .bases import AssignmentPrecedence, NextStateConditional
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from . import sw_onread
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from . import sw_onwrite
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from . import sw_singlepulse
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from . import hw_write
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from . import hw_set_clr
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@@ -189,6 +190,8 @@ class FieldLogic:
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self.add_sw_conditional(sw_onwrite.WriteSet(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.Write(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_singlepulse.Singlepulse(self.exp), AssignmentPrecedence.SW_SINGLEPULSE)
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self.add_hw_conditional(hw_write.AlwaysWrite(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_write.WELWrite(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_write.WEWrite(self.exp), AssignmentPrecedence.HW_WRITE)
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@@ -24,6 +24,7 @@ class AssignmentPrecedence(enum.IntEnum):
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# Software access assignment groups
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SW_ONREAD = 5000
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SW_ONWRITE = 4000
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SW_SINGLEPULSE = 3000
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# Hardware access assignment groups
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HW_WRITE = 3000
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23
peakrdl/regblock/field_logic/sw_singlepulse.py
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23
peakrdl/regblock/field_logic/sw_singlepulse.py
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@@ -0,0 +1,23 @@
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from typing import TYPE_CHECKING, List
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from .bases import NextStateConditional
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if TYPE_CHECKING:
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from systemrdl.node import FieldNode
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class Singlepulse(NextStateConditional):
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comment = "singlepulse clears back to 0"
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def is_match(self, field: 'FieldNode') -> bool:
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return field.get_property('singlepulse')
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def get_predicate(self, field: 'FieldNode') -> str:
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# TODO: make exporter promote this to an "else"?
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# Be mindful of sw/hw precedence. this would have to come last regardless
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return "1"
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def get_assignments(self, field: 'FieldNode') -> List[str]:
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field_path = self.get_field_path(field)
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return [
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f"field_combo.{field_path}.next = '0;",
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f"field_combo.{field_path}.load_next = '1;",
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]
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