bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add singlepulse support

Browse Source
This commit is contained in:
Alex Mykyta
2021-12-05 23:09:33 -08:00
parent 027ac99ead
commit f5b12253ad
8 changed files with 97 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
peakrdl/regblock/field_logic/__init__.py
View File

@@ -5,6 +5,7 @@ from systemrdl.rdltypes import PropertyReference, PrecedenceType
from .bases import AssignmentPrecedence, NextStateConditional
from . import sw_onread
from . import sw_onwrite
from . import sw_singlepulse
from . import hw_write
from . import hw_set_clr
@@ -189,6 +190,8 @@ class FieldLogic:
self.add_sw_conditional(sw_onwrite.WriteSet(self.exp), AssignmentPrecedence.SW_ONWRITE)
self.add_sw_conditional(sw_onwrite.Write(self.exp), AssignmentPrecedence.SW_ONWRITE)
self.add_sw_conditional(sw_singlepulse.Singlepulse(self.exp), AssignmentPrecedence.SW_SINGLEPULSE)
self.add_hw_conditional(hw_write.AlwaysWrite(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_write.WELWrite(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_write.WEWrite(self.exp), AssignmentPrecedence.HW_WRITE)