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Alex Mykyta
2021-11-21 19:00:47 -08:00
parent d3c876a491
commit f70bdf774c
69 changed files with 1730 additions and 403 deletions
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26
doc/conf.py
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@@ -29,7 +29,9 @@ author = 'Alex Mykyta'
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
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]
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templates_path = ['_templates']
@@ -50,4 +52,26 @@ html_theme = "sphinx_rtd_theme"
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
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doc/index.rst
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@@ -1,20 +1,14 @@
.. PeakRDL-regblock documentation master file, created by
sphinx-quickstart on Tue Nov 16 23:25:58 2021.
You can adapt this file completely to your liking, but it should at least
contain the root `toctree` directive.
Welcome to PeakRDL-regblock's documentation!
============================================
.. toctree::
:maxdepth: 2
:caption: Contents:
:hidden:
:caption: Property Support
Indices and tables
==================
* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`
props/field
props/reg
props/addrmap
props/signal
props/rhs_props
limitations

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doc/limitations.rst Normal file
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@@ -0,0 +1,27 @@
Known Issues & Limitations
==========================
Not all SystemRDL features are supported by this exporter. For a listing of
supported properties, see the appropriate property listing page in the previous
sections.
External Components
-------------------
Regfiles, registers & fields instantiated using the ``external`` keyword are not supported yet.
Alias Registers
---------------
Registers instantiated using the ``alias`` keyword are not supported yet.
Unaligned Registers
-------------------
All address offsets & strides shall be a multiple of the regwidth used. Specifically:
* Each register's address and array stride shall be aligned to it's regwidth.
* Each regfile or addrmap shall use an offset and stride that is a multiple of the largest regwidth it encloses.

54
doc/logbooks/000-Main-Logbook
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@@ -76,6 +76,60 @@ Write about this in the SystemRDL errata?
Maybe add some words to the "clarifications" section
================================================================================
Unit Testing
================================================================================
I NEED to start building a suite of unit-tests!
Goal:
- Small easy-to-understand testcases
- Parameterized testcases to rerun testcases with different cpuifs, etc.
- coverage
Split it into the following components:
Common testbench SV infrastructure
Make a generic SV framework that can be re-used everywhere
Use SV interfaces/classes and even `include preprocessor tricks to make it possible
to swap out for specific testcases:
- cpuif abstraction layer
Need to be able to swap out to different CPU interfaces easily
- Clocks/resets
- DUT instantiation
Will need to account for minor variations in port list somehow
Maybe a good time to use the .* method?
- Helper functions, assertion library, etc.
Testcase-specific
SV sequence file that issues transactions and asserts things
Dispatch tests completely through pytest
- Each testcase has its own folder with:
testcase-specific SV file(s)
RDL file
pytest entry point .py file
- build up py utility functions that will:
Export the testcase-specific RDL --> SV
Compile and run the simulation
need to deal with timeouts if the RTL deadlocks somehow. Limit of how many uS to run?
Query sim result for pass/fail
- Each testcase folder will likely have multiple subtests
- Variations to RDL export:
- different cpuif
- pipe stages
- etc.
- Different test sequences
may be necessary to test the same compilation in different ways
I can imagine it may not be possible to do everything from a single test sequence.
May require the sim to reset to T-0 for fresh-slate.
- Handle these variations using pytest testcases & parameterizations as appropriate.
Possibly something like:
- Each pytest class --> unique compilation/elaboration
pytest parameters to expand this for export variations
- Each pytest class method --> simulation sequence
- Collect coverage!
install the tool in a venv, collect exporter coverage, etc.
TBD if i want to deal with SV coverage (is that even allowed in modelsim free?)
================================================================================
Dev Todo list
================================================================================

2
doc/logbooks/Signal Dereferencer
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@@ -4,7 +4,7 @@ to stuff via a normalized interface.
For example, if RDL defines:
my_field->next = my_other_field
Then in Python (or a template) I could do:
x = my_field.get_property("next")
x = my_field.get_property('next')
y = dereferencer.get(x)
and trust that I'll get a value/identifier/whatever that accurately represents
the value being referenced

12
doc/logbooks/Validation Needed
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@@ -82,7 +82,7 @@ X If a node ispresent=true, and any of it's properties are a reference,
then those references' ispresent shall also be true
This is an explicit clause in the spec: 5.3.1-i
! Flag illegal sw actions if not readable/writable
X Flag illegal sw actions if not readable/writable
The following combinations dont get flagged currently:
sw=w; rclr;
sw=w; rset;
@@ -91,15 +91,15 @@ X If a node ispresent=true, and any of it's properties are a reference,
their counterparts do get flagged. such as:
sw=w; onread=rclr;
X Signals marked as field_reset or cpuif_reset need to have activehigh/activelow
specified. (8.2.1-d states that activehigh/low does not have an implied default state if unset!)
Also aplies to signals referenced by resetsignal
! hwclr/hwset/we/wel probably shouldn't be able to reference itself
y->hwclr = y;
y->we = y;
... it works, but should it be allowed? Seems like user-error
! Signals marked as field_reset or cpuif_reset need to have activehigh/activelow
specified. (8.2.1-d states that activehigh/low does not have an implied default state if unset!)
Also aplies to signals referenced by fieldreset
@@ -126,7 +126,7 @@ X Warn/error on any signal with cpuif_reset set, that is not in the top-level
! async data signals
Only supporting async signals if they are exclusively used in resets.
Anyhting else declared as "async" shall be an error
Anyhting else declared as "async" shall emit a warning that it is ignored
I have zero interest in implementing resynchronizers
! Error if a property references a non-signal component, or property reference from

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Addrmap/Regfile Properties
==========================
.. note:: Any properties not explicitly listed here are either implicitly supported,
or are not relevant to the regblock exporter and are ignored.
errextbus
---------
|NO|
sharedextbus
------------
|NO|
Addrmap Properties
==================
bigendian/littleendian
----------------------
|NO|
bridge
------
|NO|
rsvdset
-------
|NO|

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@@ -0,0 +1,276 @@
Field Properties
================
.. note:: Any properties not explicitly listed here are either implicitly supported,
or are not relevant to the regblock exporter and are ignored.
Software Access Properties
--------------------------
onread/onwrite
^^^^^^^^^^^^^^
|EX|
rclr/rset
^^^^^^^^^
See ``onread``
singlepulse
^^^^^^^^^^^
|NO|
sw
^^^
|OK|
swacc
^^^^^
|EX|
If true, infers an output signal ``swacc`` that is asserted as the field is sampled for a software read operation.
.. wavedrom::
{signal: [
{name: 'clk', wave: 'p....'},
{name: 'hwif_in..value', wave: 'x.=x.', data: ['D']},
{name: 'hwif_out..swacc', wave: '0.10.'}
]}
swmod
^^^^^
|EX|
If true, infers an output signal ``swmod`` that is asserted as the field is being modified by software.
.. wavedrom::
{signal: [
{name: 'clk', wave: 'p.....'},
{name: 'hwif_out..value', wave: '=..=..', data: ['old', 'new']},
{name: 'hwif_out..swmod', wave: '0.10..'}
]}
swwe/swwel
^^^^^^^^^^
TODO: Describe result
boolean
|NO|
bit
|NO|
reference
|NO|
woclr/woset
^^^^^^^^^^^
See ``onwrite``
Hardware Access Properties
--------------------------
anded/ored/xored
^^^^^^^^^^^^^^^^
|EX|
hw
^^^
|OK|
hwclr/hwset
^^^^^^^^^^^
boolean
|EX|
reference
|EX|
hwenable/hwmask
^^^^^^^^^^^^^^^
|EX|
we/wel
^^^^^^
Write-enable control from hardware interface
.. wavedrom::
{signal: [
{name: 'clk', wave: 'p....'},
{name: 'hwif_in..value', wave: 'x.=x.', data: ['D']},
{name: 'hwif_in..we', wave: '0.10.',},
{name: 'hwif_in..wel', wave: '1.01.',},
{name: '<field value>', wave: 'x..=.', data: ['D']}
]}
boolean
|OK|
if set, infers the existence of input signal ``hwif_in..we`` or ``hwif_in..wel``
reference
|EX|
Counter Properties
------------------
counter
^^^^^^^
|NO|
decr
^^^^
reference
|NO|
decrthreshold
^^^^^^^^^^^^^
boolean
|NO|
bit
|NO|
reference
|NO|
decrsaturate
^^^^^^^^^^^^
boolean
|NO|
bit
|NO|
reference
|NO|
decrvalue
^^^^^^^^^
bit
|NO|
reference
|NO|
decrwidth
^^^^^^^^^
|NO|
incr
^^^^
|NO|
incrsaturate/saturate
^^^^^^^^^^^^^^^^^^^^^
boolean
|NO|
bit
|NO|
reference
|NO|
incrthreshold/threshold
^^^^^^^^^^^^^^^^^^^^^^^
boolean
|NO|
bit
|NO|
reference
|NO|
incrvalue
^^^^^^^^^
bit
|NO|
reference
|NO|
incrwidth
^^^^^^^^^
|NO|
overflow
^^^^^^^^
|NO|
underflow
^^^^^^^^^
|NO|
Interrupt Properties
--------------------
enable
^^^^^^
|NO|
haltenable
^^^^^^^^^^
|NO|
haltmask
^^^^^^^^
|NO|
intr
^^^^
|NO|
mask
^^^^
|NO|
sticky
^^^^^^
|NO|
stickybit
^^^^^^^^^
|NO|
Misc
----
encode
^^^^^^
|NO|
next
^^^^
|NO|
paritycheck
^^^^^^^^^^^
|NO|
precedence
^^^^^^^^^^
|EX|
reset
^^^^^
bit
|OK|
reference
|EX|
resetsignal
^^^^^^^^^^^
|EX|

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Register Properties
===================
.. note:: Any properties not explicitly listed here are either implicitly supported,
or are not relevant to the regblock exporter and are ignored.
accesswidth
-----------
|NO|
Only ``accesswidth`` that is equal to the ``regwidth`` is supported (default if unset)
regwidth
--------
|OK|
shared
------
|NO|

114
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@@ -0,0 +1,114 @@
RHS Property References
=======================
Field
-----
swacc
^^^^^
|EX|
swmod
^^^^^
|EX|
swwe/swwel
^^^^^^^^^^
|EX|
anded/ored/xored
^^^^^^^^^^^^^^^^
|EX|
hwclr/hwset
^^^^^^^^^^^
|EX|
hwenable/hwmask
^^^^^^^^^^^^^^^
|EX|
we/wel
^^^^^^
|EX|
decr
^^^^
|NO|
decrthreshold
^^^^^^^^^^^^^
|NO|
decrsaturate
^^^^^^^^^^^^
|NO|
decrvalue
^^^^^^^^^
|EX|
incr
^^^^
|NO|
incrsaturate/saturate
^^^^^^^^^^^^^^^^^^^^^
|NO|
incrthreshold/threshold
^^^^^^^^^^^^^^^^^^^^^^^
|NO|
incrvalue
^^^^^^^^^
|EX|
overflow
^^^^^^^^
|NO|
underflow
^^^^^^^^^
|NO|
enable
^^^^^^
|EX|
haltenable
^^^^^^^^^^
|EX|
haltmask
^^^^^^^^
|EX|
mask
^^^^
|EX|
next
^^^^
|EX|
reset
^^^^^
|EX|
resetsignal
^^^^^^^^^^^
|EX|
Register
--------
intr
^^^^
|NO|
halt
^^^^
|NO|

25
doc/props/signal.rst Normal file
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@@ -0,0 +1,25 @@
Signal Properties
=================
.. note:: Any properties not explicitly listed here are either implicitly supported,
or are not relevant to the regblock exporter and are ignored.
activehigh/activelow
--------------------
|EX|
sync/async
----------
|EX|
Only supported for signals used as resets to infer edge-sensitive reset.
Ignored in all other contexts.
cpuif_reset
-----------
|EX|
field_reset
-----------
|EX|

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@@ -1 +1,2 @@
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