testcase framework

2021-11-21 19:00:47 -08:00
parent d3c876a491
commit f70bdf774c
69 changed files with 1730 additions and 403 deletions
--- a/peakrdl/regblock/cpuif/apb3/init.py
+++ b/peakrdl/regblock/cpuif/apb3/init.py
@@ -14,7 +14,6 @@ class APB3_Cpuif(CpuifBase):
 class APB3_Cpuif_flattened(APB3_Cpuif):
    @property
    def port_declaration(self) -> str:
-        # TODO: Reference data/addr width from verilog parameter perhaps?
        lines = [
            "input wire " + self.signal("psel"),
            "input wire " + self.signal("penable"),