testcase framework

2021-11-21 19:00:47 -08:00
parent d3c876a491
commit f70bdf774c
69 changed files with 1730 additions and 403 deletions
--- a/peakrdl/regblock/scan_design.py
+++ b/peakrdl/regblock/scan_design.py
@@ -22,7 +22,7 @@ class DesignScanner(RDLListener):

    def enter_Reg(self, node: 'RegNode') -> None:
        # The CPUIF's bus width is sized according to the largest register in the design
-        self.cpuif_data_width = max(self.cpuif_data_width, node.get_property("regwidth"))
+        self.cpuif_data_width = max(self.cpuif_data_width, node.get_property('regwidth'))

    # TODO: Collect any references to signals that lie outside of the hierarchy
    # These will be added as top-level signals