testcase framework
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232
test/lib/regblock_testcase.py
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232
test/lib/regblock_testcase.py
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from typing import Optional, List
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import unittest
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import os
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import glob
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import shutil
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import subprocess
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import inspect
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import pytest
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import jinja2 as jj
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from systemrdl import RDLCompiler
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from peakrdl.regblock import RegblockExporter
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from .cpuifs.base import CpuifTestMode
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from .cpuifs.apb3 import APB3
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class RegblockTestCase(unittest.TestCase):
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#: Path to the testcase's RDL file.
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#: Relative to the testcase's dir. If unset, the first RDL file found in the
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#: testcase dir will be used
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rdl_file = None # type: Optional[str]
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#: RDL type name to elaborate. If unset, compiler will automatically choose
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#: the top.
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rdl_elab_target = None # type: Optional[str]
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#: Parameters to pass into RDL elaboration
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rdl_elab_params = {}
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#: Define what CPUIF to use for this testcase
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cpuif = APB3() # type: CpuifTestMode
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# Other exporter args:
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retime_read_fanin = False
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retime_read_response = False
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#: Abort test if it exceeds this number of clock cycles
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timeout_clk_cycles = 1000
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#: this gets auto-loaded via the _load_request autouse fixture
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request = None # type: pytest.FixtureRequest
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@pytest.fixture(autouse=True)
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def _load_request(self, request):
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self.request = request
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@classmethod
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def get_testcase_dir(cls) -> str:
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class_dir = os.path.dirname(inspect.getfile(cls))
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return class_dir
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@classmethod
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def get_build_dir(cls) -> str:
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this_dir = cls.get_testcase_dir()
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build_dir = os.path.join(this_dir, cls.__name__ + ".out")
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return build_dir
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@classmethod
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def _write_params(cls) -> None:
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"""
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Write out the class parameters to a file so that it is easier to debug
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how a testcase was parameterized
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"""
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path = os.path.join(cls.get_build_dir(), "params.txt")
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with open(path, 'w') as f:
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for k, v in cls.__dict__.items():
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if k.startswith("_") or callable(v):
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continue
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f.write(f"{k}: {repr(v)}\n")
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@classmethod
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def _export_regblock(cls) -> RegblockExporter:
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"""
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Call the peakrdl.regblock exporter to generate the DUT
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"""
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this_dir = cls.get_testcase_dir()
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if cls.rdl_file:
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rdl_file = cls.rdl_file
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else:
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# Find any *.rdl file in testcase dir
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rdl_file = glob.glob(os.path.join(this_dir, "*.rdl"))[0]
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rdlc = RDLCompiler()
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rdlc.compile_file(rdl_file)
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root = rdlc.elaborate(cls.rdl_elab_target, "regblock", cls.rdl_elab_params)
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exporter = RegblockExporter()
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exporter.export(
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root,
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cls.get_build_dir(),
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module_name="regblock",
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package_name="regblock_pkg",
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cpuif_cls=cls.cpuif.cpuif_cls,
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retime_read_fanin=cls.retime_read_fanin,
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retime_read_response=cls.retime_read_response,
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)
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return exporter
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@classmethod
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def _generate_tb(cls, exporter: RegblockExporter):
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"""
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Render the testbench template into actual tb.sv
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"""
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template_root_path = os.path.join(os.path.dirname(__file__), "..")
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loader = jj.FileSystemLoader(
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template_root_path
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)
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jj_env = jj.Environment(
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loader=loader,
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undefined=jj.StrictUndefined,
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)
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context = {
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"cls": cls,
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"exporter": exporter,
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}
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# template path needs to be relative to the Jinja loader root
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template_path = os.path.join(cls.get_testcase_dir(), "tb.sv")
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template_path = os.path.relpath(template_path, template_root_path)
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template = jj_env.get_template(template_path)
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output_path = os.path.join(cls.get_build_dir(), "tb.sv")
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stream = template.stream(context)
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stream.dump(output_path)
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@classmethod
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def _compile_tb(cls):
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# CD into the build directory
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cwd = os.getcwd()
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os.chdir(cls.get_build_dir())
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cmd = [
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"vlog", "-sv", "-quiet", "-l", "build.log",
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# Free version of ModelSim throws errors if generate/endgenerate
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# blocks are not used.
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# These have been made optional long ago. Modern versions of SystemVerilog do
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# not require them and I prefer not to add them.
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"-suppress", "2720",
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# Ignore noisy warning about vopt-time checking of always_comb/always_latch
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"-suppress", "2583",
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]
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# Add CPUIF sources
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cmd.extend(cls.cpuif.get_tb_files())
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# Add DUT sources
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cmd.append("regblock_pkg.sv")
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cmd.append("regblock.sv")
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# Add TB
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cmd.append("tb.sv")
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# Run command!
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try:
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subprocess.run(cmd, check=True)
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finally:
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# cd back
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os.chdir(cwd)
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@classmethod
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def setUpClass(cls):
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# Create fresh build dir
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build_dir = cls.get_build_dir()
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if os.path.exists(build_dir):
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shutil.rmtree(build_dir)
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os.mkdir(build_dir)
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cls._write_params()
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# Convert testcase RDL file --> SV
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exporter = cls._export_regblock()
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# Create testbench from template
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cls._generate_tb(exporter)
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cls._compile_tb()
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def setUp(self) -> None:
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# cd into the build directory
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self.original_cwd = os.getcwd()
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os.chdir(self.get_build_dir())
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def run_test(self, plusargs:List[str] = None) -> None:
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plusargs = plusargs or []
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test_name = self.request.node.name
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# call vsim
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cmd = [
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"vsim", "-quiet",
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"-msgmode", "both",
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"-do", "set WildcardFilter [lsearch -not -all -inline $WildcardFilter Memory]",
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"-do", "log -r /*;",
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"-do", "run -all; exit;",
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"-c",
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"-l", "%s.log" % test_name,
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"-wlf", "%s.wlf" % test_name,
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"tb",
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]
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for plusarg in plusargs:
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cmd.append("+" + plusarg)
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subprocess.run(cmd, check=True)
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self.assertSimLogPass("%s.log" % test_name)
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def tearDown(self) -> None:
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# cd back
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os.chdir(self.original_cwd)
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def assertSimLogPass(self, path: str):
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self.assertTrue(os.path.isfile(path))
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with open(path, encoding="utf-8") as f:
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for line in f:
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if line.startswith("# ** Error"):
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self.fail(line)
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elif line.startswith("# ** Fatal"):
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self.fail(line)
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