Add Intel Avalon MM cpuif. #40

src/peakrdl_regblock/__peakrdl__.py

@@ -6,7 +6,7 @@ from peakrdl.plugins.exporter import ExporterSubcommandPlugin #pylint: disable=i
 from peakrdl.config import schema #pylint: disable=import-error
 
 from .exporter import RegblockExporter
-from .cpuif import apb3, apb4, axi4lite, passthrough, CpuifBase
+from .cpuif import CpuifBase, apb3, apb4, axi4lite, passthrough, avalon
 from .udps import ALL_UDPS
 from . import entry_points
 
@@ -48,13 +48,15 @@ class Exporter(ExporterSubcommandPlugin):
 
         # All built-in CPUIFs
         cpuifs = {
+            "passthrough": passthrough.PassthroughCpuif,
             "apb3": apb3.APB3_Cpuif,
             "apb3-flat": apb3.APB3_Cpuif_flattened,
             "apb4": apb4.APB4_Cpuif,
             "apb4-flat": apb4.APB4_Cpuif_flattened,
             "axi4-lite": axi4lite.AXI4Lite_Cpuif,
             "axi4-lite-flat": axi4lite.AXI4Lite_Cpuif_flattened,
-            "passthrough": passthrough.PassthroughCpuif
+            "avalon-mm": avalon.Avalon_Cpuif,
+            "avalon-mm-flat": avalon.Avalon_Cpuif_flattened,
         }
 
         # Load any cpuifs specified via entry points

src/peakrdl_regblock/cpuif/avalon/__init__.py

@@ -0,0 +1,37 @@
+from ..base import CpuifBase
+from ...utils import clog2
+
+class Avalon_Cpuif(CpuifBase):
+    template_path = "avalon_tmpl.sv"
+
+    @property
+    def port_declaration(self) -> str:
+        return "avalon_mm_intf.agent avalon"
+
+    def signal(self, name:str) -> str:
+        return "avalon." + name
+
+    @property
+    def word_addr_width(self) -> int:
+        # Avalon agents use word addressing, therefore address width is reduced
+        return self.addr_width - clog2(self.data_width_bytes)
+
+class Avalon_Cpuif_flattened(Avalon_Cpuif):
+    @property
+    def port_declaration(self) -> str:
+        lines = [
+            "input wire " + self.signal("read"),
+            "input wire " + self.signal("write"),
+            "output logic " + self.signal("waitrequest"),
+            f"input wire [{self.word_addr_width-1}:0] " + self.signal("address"),
+            f"input wire [{self.data_width-1}:0] " + self.signal("writedata"),
+            f"input wire [{self.data_width_bytes-1}:0] " + self.signal("byteenable"),
+            "output logic " + self.signal("readdatavalid"),
+            "output logic " + self.signal("writeresponsevalid"),
+            f"output logic [{self.data_width-1}:0] " + self.signal("readdata"),
+            "output logic [1:0] " + self.signal("response"),
+        ]
+        return ",\n".join(lines)
+
+    def signal(self, name:str) -> str:
+        return "avalon_" + name

src/peakrdl_regblock/cpuif/avalon/avalon_tmpl.sv

@@ -0,0 +1,29 @@
+// Request
+always_comb begin
+    cpuif_req = {{cpuif.signal("read")}} | {{cpuif.signal("write")}};
+    cpuif_req_is_wr = {{cpuif.signal("write")}};
+    {%- if cpuif.data_width_bytes == 1 %}
+    cpuif_addr = {{cpuif.signal("address")}};
+    {%- else %}
+    cpuif_addr = { {{-cpuif.signal("address")}}, {{clog2(cpuif.data_width_bytes)}}'b0};
+    {%- endif %}
+    cpuif_wr_data = {{cpuif.signal("writedata")}};
+    for(int i=0; i<{{cpuif.data_width_bytes}}; i++) begin
+        cpuif_wr_biten[i*8 +: 8] <= {8{ {{-cpuif.signal("byteenable")}}[i]}};
+    end
+    {{cpuif.signal("waitrequest")}} = (cpuif_req_stall_rd & {{cpuif.signal("read")}}) | (cpuif_req_stall_wr & {{cpuif.signal("write")}});
+end
+
+// Response
+always_comb begin
+    {{cpuif.signal("readdatavalid")}} = cpuif_rd_ack;
+    {{cpuif.signal("writeresponsevalid")}} = cpuif_wr_ack;
+    {{cpuif.signal("readdata")}} = cpuif_rd_data;
+    if(cpuif_rd_err || cpuif_wr_err) begin
+        // SLVERR
+        {{cpuif.signal("response")}} = 2'b10;
+    end else begin
+        // OK
+        {{cpuif.signal("response")}} = 2'b00;
+    end
+end