Add Intel Avalon MM cpuif. #40

tests/test_structural_sw_rw/testcase.py

@@ -1,18 +1,37 @@
 import os
 
 from parameterized import parameterized_class
+import pytest
 
 from ..lib.sim_testcase import SimTestCase
 from ..lib.synth_testcase import SynthTestCase
-from ..lib.test_params import TEST_PARAMS, get_permutations
+from ..lib.test_params import get_permutations
+from ..lib.cpuifs import ALL_CPUIF
 from ..lib.simulators.xilinx import Xilinx
-import pytest
 
-@parameterized_class(TEST_PARAMS)
-class TestParameterizations(SimTestCase):
+
+
+
+@parameterized_class(get_permutations({
+    "cpuif": ALL_CPUIF,
+    "retime_read_fanin": [True, False],
+    "retime_read_response": [True, False],
+}))
+class TestCPUIFS(SimTestCase):
     def test_dut(self):
         self.run_test()
 
+
+
+@parameterized_class(get_permutations({
+    "reuse_hwif_typedefs": [True, False],
+}))
+class TestTypedefs(SimTestCase):
+    def test_dut(self):
+        self.run_test()
+
+
+
 @parameterized_class(get_permutations({
     "default_reset_activelow": [True, False],
     "default_reset_async": [True, False],
@@ -22,14 +41,26 @@ class TestDefaultResets(SimTestCase):
         self.run_test()
 
 
-@parameterized_class(TEST_PARAMS)
+
+@parameterized_class(get_permutations({
+    "cpuif": ALL_CPUIF,
+    "retime_read_fanin": [True, False],
+    "retime_read_response": [True, False],
+    "reuse_hwif_typedefs": [True, False],
+}))
 class TestSynth(SynthTestCase):
     def test_dut(self):
         self.run_synth()
 
 
+
 @pytest.mark.skipif(os.environ.get("STUB_SIMULATOR", False) or os.environ.get("NO_XSIM", False), reason="user skipped")
-@parameterized_class(TEST_PARAMS)
+@parameterized_class(get_permutations({
+    "cpuif": ALL_CPUIF,
+    "retime_read_fanin": [True, False],
+    "retime_read_response": [True, False],
+    "reuse_hwif_typedefs": [True, False],
+}))
 class TestVivado(SimTestCase):
     """
     Vivado XSIM's implementation of clocking blocks is broken, which is heavily used