addrmap top {
    default regwidth = 32;
    default sw=rw;
    default hw=na;

    // Internal registers
    reg {
        field {
            sw=rw; hw=na; // Storage element
        } f[31:0] = 40;
    } r_rw;

    reg {
        field {
            sw=r; hw=na; // Wire/Bus - constant value
        } f[31:0] = 80;
    } r_ro;

    reg {
        field {
            sw=w; hw=r; // Storage element
        } f[31:0] = 100;
    } r_wo;

    // Combined read-only and write-only register
    reg {
        default sw = w;
        default hw = r;
        field {} wvalue[32] = 0;
    } writeonly @ 0x1C;
    reg {
        default sw = r;
        default hw = na;
        field {} rvalue[32] = 200;
    } readonly @ 0x1C;

    // External memories
    external mem {
        memwidth = 32;
        mementries = 2;
    } mem_rw @ 0x20;

    external mem {
        memwidth = 32;
        mementries = 2;
        sw=r;
    } mem_ro @ 0x28;

    external mem {
        memwidth = 32;
        mementries = 2;
        sw=w;
    } mem_wo @ 0x30;

    // External block
    external regfile {
      // Placeholder registers
      reg {
          field {
              sw=rw; hw=na;
          } f[31:0] = 40;
      } r_rw;

      reg {
          field {
              sw=r; hw=na;
          } f[31:0] = 80;
      } r_ro;

      reg {
          field {
              sw=w; hw=r;
          } f[31:0] = 100;
      } r_wo;
    } external_rf @ 0x40;
};