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Signal wrapper classes
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Define a signal wrapper class that is easier to use in templates.

Provides the following properties:
    .is_async
    .is_activehigh
    .identifier
        Returns the Verilog identifier string for this signal
    .activehigh_identifier
        Normalizes identifier to active-high logic
        same as .identifier, but prepends '~' if is_activehigh = False
    .width

Default reset class instance:
    Extends the base class
    Hardcodes as follows:
        .is_async = True
        .is_activehigh = True
        .identifier = "rst"
        .width = 1

Wrapper classes
    Wrap around a systemrdl.SignalNode


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CPU Interface Class
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Entry point class for a given CPU interface type (APB, AXI, etc..)

Does the following:
    - Provide linkage to the logic implementation Jinja template
    - Interface signal identifier properties
        Aliases for signal identifiers to allow flat or sv-interface style
        eg:
            self.psel --> "s_apb_psel" or "s_apb.psel"
        if sv interface, use the interface name class prpoerty
    - Port declaration text property
        declare as sv interface, or flat port list
        If flattened, should use signal identifier properties
        If sv interface, I should breakout the interface & modport name as
        class properties for easy user-override