79 lines
2.9 KiB
ReStructuredText
79 lines
2.9 KiB
ReStructuredText
Customizing the CPU interface
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=============================
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Use your own existing SystemVerilog interface definition
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--------------------------------------------------------
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This exporter comes pre-bundled with its own SystemVerilog interface declarations.
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What if you already have your own SystemVerilog interface declaration that you prefer?
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Not a problem! As long as your interface definition is similar enough, it is easy
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to customize and existing CPUIF definition.
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As an example, let's use the SystemVerilog interface definition for
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:ref:`cpuif_axi4lite` that is bundled with this project. This interface uses
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following style and naming conventions:
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* SystemVerilog interface type name is ``axi4lite_intf``
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* Defines modports named ``master`` and ``slave``
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* Interface signals are all upper-case: ``AWREADY``, ``AWVALID``, etc...
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Lets assume your preferred SV interface definition uses a slightly different naming convention:
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* SystemVerilog interface type name is ``axi4_lite_interface``
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* Modports are capitalized and use suffixes ``Master_mp`` and ``Slave_mp``
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* Interface signals are all lower-case: ``awready``, ``awvalid``, etc...
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Rather than rewriting a new CPU interface definition, you can extend and adjust the existing one:
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.. code-block:: python
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from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif
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class My_AXI4Lite(AXI4Lite_Cpuif):
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@property
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def port_declaration(self) -> str:
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# Override the port declaration text to use the alternate interface name and modport style
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return "axi4_lite_interface.Slave_mp s_axil"
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def signal(self, name:str) -> str:
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# Override the signal names to be lowercase instead
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return "s_axil." + name.lower()
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Then use your custom CPUIF during export:
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.. code-block:: python
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exporter = RegblockExporter()
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exporter.export(
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root, "path/to/output_dir",
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cpuif_cls=My_AXI4Lite
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)
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Custom CPU Interface Protocol
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-----------------------------
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If you require a CPU interface protocol that is not included in this project,
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you can define your own.
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1. Create a SystemVerilog CPUIF implementation template file.
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This contains the SystemVerilog implementation of the bus protocol. The logic
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in this shall implement a translation between your custom protocol and the
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:ref:`cpuif_protocol`.
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Reminder that this template will be preprocessed using Jinja, so you can use
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some templating tags to dynamically render content. See the implementations of
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existing CPU interfaces as an example.
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2. Create a Python class that defines your CPUIF
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Extend your class from :class:`peakrdl_regblock.cpuif.CpuifBase`.
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Define the port declaration string, and provide a reference to your template file.
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3. Use your new CPUIF definition when exporting.
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4. If you think the CPUIF protocol is something others might find useful, let me know and I can add it to PeakRDL!
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