91 lines
2.8 KiB
Systemverilog
91 lines
2.8 KiB
Systemverilog
{%- import "utils_tmpl.sv" as utils with context -%}
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{{hwif.get_package_declaration()}}
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module {{module_name}} #(
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// TODO: pipeline parameters
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)(
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input wire clk,
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{%- for signal in reset_signals %}
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{{signal.port_declaration}},
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{% endfor %}
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{%- for signal in user_signals %}
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{{signal.port_declaration}},
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{% endfor %}
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{%- for interrupt in interrupts %}
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{{interrupt.port_declaration}},
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{% endfor %}
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{{cpuif.port_declaration|indent(8)}},
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{{hwif.port_declaration|indent(8)}}
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);
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localparam ADDR_WIDTH = {{addr_width}};
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localparam DATA_WIDTH = {{data_width}};
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//--------------------------------------------------------------------------
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// CPU Bus interface logic
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//--------------------------------------------------------------------------
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logic cpuif_req;
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logic cpuif_req_is_wr;
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logic [ADDR_WIDTH-1:0] cpuif_addr;
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logic [DATA_WIDTH-1:0] cpuif_wr_data;
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logic [DATA_WIDTH-1:0] cpuif_wr_bitstrb;
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logic cpuif_rd_ack;
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logic [DATA_WIDTH-1:0] cpuif_rd_data;
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logic cpuif_rd_err;
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logic cpuif_wr_ack;
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logic cpuif_wr_err;
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{{cpuif.get_implementation()|indent}}
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//--------------------------------------------------------------------------
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// Address Decode
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//--------------------------------------------------------------------------
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{{address_decode.get_strobe_struct()|indent}}
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access_strb_t access_strb;
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always_comb begin
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{{address_decode.get_implementation()|indent(8)}}
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end
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// Writes are always posted with no error response
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assign cpuif_wr_ack = cpuif_req & cpuif_req_is_wr;
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assign cpuif_wr_err = '0;
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//--------------------------------------------------------------------------
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// Field logic
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//--------------------------------------------------------------------------
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{{field_logic.get_storage_struct()|indent}}
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// TODO: Field next-state logic, and output port signal assignment (aka output mapping layer)
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{{field_logic.get_implementation()|indent}}
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//--------------------------------------------------------------------------
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// Readback mux
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//--------------------------------------------------------------------------
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logic readback_err;
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logic readback_done;
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logic [DATA_WIDTH-1:0] readback_data;
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{{readback_mux.get_implementation()|indent}}
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{%- call utils.AlwaysFF(cpuif_reset) %}
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if({{cpuif_reset.activehigh_identifier}}) begin
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cpuif_rd_ack <= '0;
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cpuif_rd_data <= '0;
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cpuif_rd_err <= '0;
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end else begin
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cpuif_rd_ack <= readback_done;
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cpuif_rd_data <= readback_data;
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cpuif_rd_err <= readback_err;
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end
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{%- endcall %}
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endmodule
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