Alex Mykyta 9a0f6772d1 Update version

2025-05-15 22:14:39 -07:00

..

cpuif

Add simulation-time width assertions to SV interfaces. #128

2025-04-11 21:14:15 -07:00

field_logic

Allow for write enable and sticky property

2025-04-10 21:45:57 -07:00

hwif

Add signed/fixedpoint properties (#140)

2025-05-15 08:48:44 -07:00

read_buffering

read_buffering & write_buffering: get_trigger's accesswidth and regwidth should be taken from trigger when trigger is of RegNode type, not from node

2024-03-20 19:15:33 -07:00

readback

Add width cast to address decode loop iterators. #92

2024-12-19 21:49:23 -08:00

udps

Add signed/fixedpoint properties (#140)

2025-05-15 08:48:44 -07:00

write_buffering

read_buffering & write_buffering: get_trigger's accesswidth and regwidth should be taken from trigger when trigger is of RegNode type, not from node

2024-03-20 19:15:33 -07:00

__about__.py

Update version

2025-05-15 22:14:39 -07:00

__init__.py

Switch to use regular non-namespaced package

2022-06-09 20:24:53 -07:00

__peakrdl__.py

Type hinting cleanup

2025-03-03 21:37:07 -08:00

addr_decode.py

Type hinting cleanup

2025-03-03 21:37:07 -08:00

dereferencer.py

Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71

2023-10-24 22:50:41 -07:00

exporter.py

Type hinting cleanup

2025-03-03 21:37:07 -08:00

external_acks.py

Omit unecessary hwif signals if an external register is read-only or write-only. #58

2023-08-02 21:38:06 -07:00

forloop_generator.py

Type hinting cleanup

2025-03-03 21:37:07 -08:00

identifier_filter.py

Add identifier filter. closes #14

2022-07-20 23:35:17 -07:00

module_tmpl.sv

Add preprocessor ifndef around RTL assertions to allow exclusion. #104

2024-12-17 22:31:30 -08:00

package_tmpl.sv

Add user parameters to regblock package. #112

2025-04-10 22:16:13 -07:00

parity.py

Add support for field paritycheck. #35

2023-05-15 22:53:17 -07:00

scan_design.py

Type hinting cleanup

2025-03-03 21:37:07 -08:00

struct_generator.py

Add signed/fixedpoint properties (#140)

2025-05-15 08:48:44 -07:00

sv_int.py

Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71

2023-10-24 22:50:41 -07:00

utils.py

Type hinting cleanup

2025-03-03 21:37:07 -08:00

validate_design.py

Emit error if field that is asynchronously reset uses a dynamic reset value. #129

2025-03-07 19:20:44 -08:00