7 lines
218 B
Systemverilog
7 lines
218 B
Systemverilog
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
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// https://github.com/SystemRDL/PeakRDL-regblock
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package {{hwif.package_name}};
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{{hwif.get_package_contents()|indent}}
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endpackage
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