82 lines
2.6 KiB
Systemverilog
82 lines
2.6 KiB
Systemverilog
// TODO: Add a banner
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module {{module_name}} (
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input wire clk,
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{%- for signal in reset_signals %}
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{{signal.port_declaration}},
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{%- endfor %}
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{%- for signal in user_signals %}
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{{signal.port_declaration}},
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{%- endfor %}
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{%- for interrupt in interrupts %}
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{{interrupt.port_declaration}},
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{%- endfor %}
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{{cpuif.port_declaration|indent(8)}}
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{%- if hwif.has_input_struct or hwif.has_output_struct %},{% endif %}
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{{hwif.port_declaration|indent(8)}}
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);
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localparam ADDR_WIDTH = {{addr_width}};
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localparam DATA_WIDTH = {{data_width}};
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//--------------------------------------------------------------------------
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// CPU Bus interface logic
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//--------------------------------------------------------------------------
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logic cpuif_req;
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logic cpuif_req_is_wr;
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logic [ADDR_WIDTH-1:0] cpuif_addr;
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logic [DATA_WIDTH-1:0] cpuif_wr_data;
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logic [DATA_WIDTH-1:0] cpuif_wr_bitstrb;
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logic cpuif_rd_ack;
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logic [DATA_WIDTH-1:0] cpuif_rd_data;
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logic cpuif_rd_err;
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logic cpuif_wr_ack;
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logic cpuif_wr_err;
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{{cpuif.get_implementation()|indent}}
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//--------------------------------------------------------------------------
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// Address Decode
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//--------------------------------------------------------------------------
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{{address_decode.get_strobe_struct()|indent}}
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decoded_reg_strb_t decoded_reg_strb;
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logic decoded_req;
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logic decoded_req_is_wr;
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logic [DATA_WIDTH-1:0] decoded_wr_data;
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logic [DATA_WIDTH-1:0] decoded_wr_bitstrb;
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always_comb begin
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{{address_decode.get_implementation()|indent(8)}}
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end
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// Writes are always granted with no error response
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assign cpuif_wr_ack = cpuif_req & cpuif_req_is_wr;
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assign cpuif_wr_err = '0;
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// Pass down signals to next stage
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assign decoded_req = cpuif_req;
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assign decoded_req_is_wr = cpuif_req_is_wr;
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assign decoded_wr_data = cpuif_wr_data;
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assign decoded_wr_bitstrb = cpuif_wr_bitstrb;
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//--------------------------------------------------------------------------
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// Field logic
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//--------------------------------------------------------------------------
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{{field_logic.get_combo_struct()|indent}}
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{{field_logic.get_storage_struct()|indent}}
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{{field_logic.get_implementation()|indent}}
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//--------------------------------------------------------------------------
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// Readback
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//--------------------------------------------------------------------------
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{{readback.get_implementation()|indent}}
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endmodule
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