46 lines
1.1 KiB
Systemverilog
46 lines
1.1 KiB
Systemverilog
{% if array_assignments is not none %}
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logic readback_err;
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logic readback_done;
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logic [DATA_WIDTH-1:0] readback_data;
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logic [DATA_WIDTH-1:0] readback_array[{{array_size}}];
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{{array_assignments}}
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always_comb begin
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automatic logic [DATA_WIDTH-1:0] readback_data_var;
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readback_done = decoded_req & ~decoded_req_is_wr;
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readback_err = '0;
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readback_data_var = '0;
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for(int i=0; i<{{array_size}}; i++) begin
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readback_data_var |= readback_array[i];
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end
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readback_data = readback_data_var;
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end
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always_ff {{get_always_ff_event(cpuif_reset)}} begin
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if({{cpuif_reset.activehigh_identifier}}) begin
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cpuif_rd_ack <= '0;
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cpuif_rd_data <= '0;
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cpuif_rd_err <= '0;
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end else begin
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cpuif_rd_ack <= readback_done;
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cpuif_rd_data <= readback_data;
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cpuif_rd_err <= readback_err;
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end
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end
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{%- else %}
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always_ff {{get_always_ff_event(cpuif_reset)}} begin
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if({{cpuif_reset.activehigh_identifier}}) begin
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cpuif_rd_ack <= '0;
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end else begin
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cpuif_rd_ack <= decoded_req & ~decoded_req_is_wr;
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end
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end
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assign cpuif_rd_data = '0;
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assign cpuif_rd_err = '0;
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{% endif %}
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