52 lines
917 B
Systemverilog
52 lines
917 B
Systemverilog
module tb;
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timeunit 1ns;
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timeprecision 1ps;
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logic rst = '1;
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logic clk = '0;
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initial forever begin
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#10ns;
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clk = ~clk;
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end
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apb3_intf apb();
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apb3_intf_driver driver(
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.clk(clk),
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.m_apb(apb)
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);
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test_regblock dut (
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.clk(clk),
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.rst(rst),
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.s_apb(apb),
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.hwif_out()
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);
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initial begin
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logic [31:0] rd_data;
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repeat(5) @(posedge clk);
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rst = '0;
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repeat(5) @(posedge clk);
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driver.read('h000, rd_data);
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driver.write('h000, 'h0);
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driver.read('h000, rd_data);
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driver.read('h100, rd_data);
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driver.write('h100, 'h0);
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driver.read('h100, rd_data);
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driver.read('h000, rd_data);
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driver.write('h000, 'hFFFF_FFFF);
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driver.read('h000, rd_data);
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repeat(5) @(posedge clk);
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$finish();
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end
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endmodule
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