bslathi19/PeakRDL-regblock
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Alex Mykyta 292aec1c6e initial dev
2021-06-01 21:57:12 -07:00
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initial dev
2021-06-01 21:57:12 -07:00
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initial dev
2021-06-01 21:57:12 -07:00
README.md
initial dev
2021-06-01 21:57:12 -07:00

README.md

PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

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Description
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Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%