300 lines
3.8 KiB
ReStructuredText
300 lines
3.8 KiB
ReStructuredText
Field Properties
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================
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.. note:: Any properties not explicitly listed here are either implicitly
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supported, or are not relevant to the regblock exporter and are ignored.
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Software Access Properties
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--------------------------
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onread/onwrite
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^^^^^^^^^^^^^^
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|OK|
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rclr/rset
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^^^^^^^^^
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See ``onread``
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singlepulse
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^^^^^^^^^^^
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|NO|
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sw
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^^^
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|OK|
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swacc
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^^^^^
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|OK|
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If true, infers an output signal ``hwif_out..swacc`` that is asserted on the
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same clock cycle that the field is being sampled during a software read
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operation.
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.. wavedrom::
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{signal: [
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{name: 'clk', wave: 'p....'},
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{name: 'hwif_in..value', wave: 'x.=x.', data: ['D']},
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{name: 'hwif_out..swacc', wave: '0.10.'}
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]}
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swmod
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^^^^^
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|OK|
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If true, infers an output signal ``hwif_out..swmod`` that is asserted as the
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field is being modified by software.
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.. wavedrom::
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{signal: [
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{name: 'clk', wave: 'p.....'},
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{name: 'hwif_out..value', wave: '=..=..', data: ['old', 'new']},
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{name: 'hwif_out..swmod', wave: '0.10..'}
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]}
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swwe/swwel
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^^^^^^^^^^
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Provides a mechanism that allows hardware to override whether the field is
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writable by software.
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boolean
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|OK|
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If True, infers an input signal ``hwif_in..swwe`` or ``hwif_in..swwel``.
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reference
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|OK|
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woclr/woset
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^^^^^^^^^^^
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See ``onwrite``
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--------------------------------------------------------------------------------
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Hardware Access Properties
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--------------------------
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anded/ored/xored
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^^^^^^^^^^^^^^^^
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|OK|
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If true, infers the existence of output signal: ``hwif_out..anded``,
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``hwif_out..ored``, ``hwif_out..xored``
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hw
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^^^
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|OK|
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hwclr/hwset
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^^^^^^^^^^^
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If both ``hwclr`` and ``hwset`` properties are used, and both are asserted at
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the same clock cycle, then ``hwset`` will take precedence.
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boolean
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|OK|
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If true, infers the existence of input signal: ``hwif_in..hwclr``, ``hwif_in..hwset``
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reference
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|OK|
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hwenable/hwmask
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^^^^^^^^^^^^^^^
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|OK|
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we/wel
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^^^^^^
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Write-enable control from hardware interface.
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If true, infers the existence of input signal: ``hwif_in..we``, ``hwif_in..wel``
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.. wavedrom::
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{signal: [
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{name: 'clk', wave: 'p....'},
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{name: 'hwif_in..value', wave: 'x.=x.', data: ['D']},
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{name: 'hwif_in..we', wave: '0.10.',},
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{name: 'hwif_in..wel', wave: '1.01.',},
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{name: '<field value>', wave: 'x..=.', data: ['D']}
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]}
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boolean
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|OK|
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If true, infers the existence of input signal ``hwif_in..we`` or ``hwif_in..wel``
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reference
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|OK|
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--------------------------------------------------------------------------------
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Counter Properties
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------------------
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counter
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^^^^^^^
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|NO|
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decr
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^^^^
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reference
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|NO|
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decrthreshold
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^^^^^^^^^^^^^
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boolean
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|NO|
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bit
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|NO|
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reference
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|NO|
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decrsaturate
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^^^^^^^^^^^^
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boolean
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|NO|
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bit
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|NO|
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reference
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|NO|
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decrvalue
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^^^^^^^^^
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bit
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|NO|
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reference
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|NO|
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decrwidth
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^^^^^^^^^
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|NO|
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incr
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^^^^
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|NO|
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incrsaturate/saturate
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^^^^^^^^^^^^^^^^^^^^^
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boolean
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|NO|
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bit
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|NO|
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reference
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|NO|
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incrthreshold/threshold
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^^^^^^^^^^^^^^^^^^^^^^^
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boolean
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|NO|
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bit
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|NO|
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reference
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|NO|
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incrvalue
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^^^^^^^^^
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bit
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|NO|
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reference
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|NO|
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incrwidth
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^^^^^^^^^
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|NO|
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overflow
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^^^^^^^^
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|NO|
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underflow
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^^^^^^^^^
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|NO|
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--------------------------------------------------------------------------------
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Interrupt Properties
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--------------------
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enable
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^^^^^^
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|NO|
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haltenable
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^^^^^^^^^^
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|NO|
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haltmask
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^^^^^^^^
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|NO|
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intr
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^^^^
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|NO|
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mask
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^^^^
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|NO|
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sticky
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^^^^^^
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|NO|
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stickybit
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^^^^^^^^^
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|NO|
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--------------------------------------------------------------------------------
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Misc
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----
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encode
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^^^^^^
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|NO|
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next
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^^^^
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|NO|
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paritycheck
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^^^^^^^^^^^
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|NO|
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precedence
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^^^^^^^^^^
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|EX|
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reset
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^^^^^
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bit
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|OK|
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reference
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|EX|
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resetsignal
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^^^^^^^^^^^
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|EX|
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