45 lines
1.1 KiB
Systemverilog
45 lines
1.1 KiB
Systemverilog
{% extends "lib/templates/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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cpuif.write('h0, 'h00);
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@cb;
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assert(cb.hwif_out.r1.f.anded == 1'b0);
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assert(cb.hwif_out.r1.f.ored == 1'b0);
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assert(cb.hwif_out.r1.f.xored == 1'b0);
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cpuif.write('h0, 'h01);
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@cb;
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assert(cb.hwif_out.r1.f.anded == 1'b0);
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assert(cb.hwif_out.r1.f.ored == 1'b1);
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assert(cb.hwif_out.r1.f.xored == 1'b1);
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cpuif.write('h0, 'h02);
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@cb;
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assert(cb.hwif_out.r1.f.anded == 1'b0);
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assert(cb.hwif_out.r1.f.ored == 1'b1);
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assert(cb.hwif_out.r1.f.xored == 1'b1);
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cpuif.write('h0, 'h03);
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@cb;
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assert(cb.hwif_out.r1.f.anded == 1'b0);
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assert(cb.hwif_out.r1.f.ored == 1'b1);
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assert(cb.hwif_out.r1.f.xored == 1'b0);
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cpuif.write('h0, 'hFE);
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@cb;
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assert(cb.hwif_out.r1.f.anded == 1'b0);
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assert(cb.hwif_out.r1.f.ored == 1'b1);
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assert(cb.hwif_out.r1.f.xored == 1'b1);
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cpuif.write('h0, 'hFF);
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@cb;
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assert(cb.hwif_out.r1.f.anded == 1'b1);
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assert(cb.hwif_out.r1.f.ored == 1'b1);
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assert(cb.hwif_out.r1.f.xored == 1'b0);
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{% endblock %}
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