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bslathi19/PeakRDL-regblock
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3d5f9d8efbf460ba86e45bb89a2cf460067e593b
PeakRDL-regblock/tests/lib
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Benjamin Davis 3d5f9d8efb Added the ability to specify a regex filter for the part-name on the synthesis tests. Implemented as --synth-part. Closes #179 (#180)
2025-11-13 20:09:03 -08:00
..
cpuifs
Error response for unmapped address or forbidden read/write access (#168)
2025-10-25 18:22:15 -07:00
simulators
Add Xcelium simulator option
2025-10-10 09:58:36 -07:00
synthesizers
Added the ability to specify a regex filter for the part-name on the synthesis tests. Implemented as --synth-part. Closes #179 (#180)
2025-11-13 20:09:03 -08:00
__init__.py
Reorganize test dir to ensure test of installed pkg
2022-02-28 23:08:41 -08:00
base_testcase.py
Error response for unmapped address or forbidden read/write access (#168)
2025-10-25 18:22:15 -07:00
external_block.sv
Simulator compatibility updates
2023-10-22 20:43:34 -07:00
external_reg.sv
Simulator compatibility updates
2023-10-22 20:43:34 -07:00
sim_testcase.py
Simulator compatibility updates
2023-10-22 20:43:34 -07:00
sv_line_anchor.py
Reorganize test dir to ensure test of installed pkg
2022-02-28 23:08:41 -08:00
synth_testcase.py
Added the ability to specify a regex filter for the part-name on the synthesis tests. Implemented as --synth-part. Closes #179 (#180)
2025-11-13 20:09:03 -08:00
tb_base.sv
Fixup test bitswap. mypy
2024-12-18 22:04:12 -08:00
test_params.py
Add Intel Avalon MM cpuif. #40
2023-05-14 17:00:55 -07:00
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