d2b4911d5f
* declared intwidth, fracwidth, and is_signed UDPs * fix boolean type name in UDP definition * generate hwif fields with fixedpoint indices * make "counter" and "encode" properties mutualy exclusive with signed/fixedpoint * add signed/unsigned to hwif * improved fixedpoint error messages, added validation tests * added fixedpoint tests * fixedpoint/signed not allowed for signal components * added signed/fixedpoint UDP docs * handle single-bit fixedpoint numbers * fix too many positional arguments lint * changed spelling of fixedpoint to fixed-point * use "logic" in place of "unsigned logic" * split signed and fixedpoint docs, added examples * allow enums with is_signed=false * split signed and fixedpoint implementations * assorted nits picked * updated is_signed validation unit test
78 lines
2.2 KiB
Systemverilog
78 lines
2.2 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{% block seq %}
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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// set all fields to all 1s
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cb.hwif_in.r1.f_Q32_n12.next <= '1;
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cb.hwif_in.r2.f_signed.next <= '1;
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cb.hwif_in.r2.f_no_sign.next <= '1;
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cpuif.write('h0, 64'hFFFF_FFFF_FFFF_FFFF);
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cpuif.write('h8, 64'hFFFF_FFFF_FFFF_FFFF);
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@cb;
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// Q8.8
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// verify bit range
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assert(cb.hwif_out.r1.f_Q8_8.value[7:-8] == '1);
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// verify bit width
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assert($size(cb.hwif_out.r1.f_Q8_8.value) == 16);
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// verfy unsigned
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assert(cb.hwif_out.r1.f_Q8_8.value > 0);
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// Q32.-12
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// verify bit range
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assert(cb.hwif_in.r1.f_Q32_n12.next[31:12] == '1);
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// verify bit width
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assert($size(cb.hwif_in.r1.f_Q32_n12.next) == 20);
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// verify unsigned
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assert(cb.hwif_in.r1.f_Q32_n12.next > 0);
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// SQ-8.32
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// verify bit range
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assert(cb.hwif_out.r1.f_SQn8_32.value[-9:-32] == '1);
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// verify bit width
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assert($size(cb.hwif_out.r1.f_SQn8_32.value) == 24);
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// verify signed
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assert(cb.hwif_out.r1.f_SQn8_32.value < 0);
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// SQ-6.7
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// verify bit range
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assert(cb.hwif_out.r1.f_SQn6_7.value[-7:-7] == '1);
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// verify bit width
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assert($size(cb.hwif_out.r1.f_SQn6_7.value) == 1);
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// verify signed
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assert(cb.hwif_out.r1.f_SQn6_7.value < 0);
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// 16-bit signed integer
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// verify bit range
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assert(cb.hwif_in.r2.f_signed.next[15:0] == '1);
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// verify bit width
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assert($size(cb.hwif_in.r2.f_signed.next) == 16);
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// verify signed
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assert(cb.hwif_in.r2.f_signed.next < 0);
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// 16-bit unsigned integer
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// verify bit range
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assert(cb.hwif_out.r2.f_unsigned.value[15:0] == '1);
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// verify bit width
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assert($size(cb.hwif_out.r2.f_unsigned.value) == 16);
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// verify unsigned
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assert(cb.hwif_out.r2.f_unsigned.value > 0);
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// 16-bit field (no sign)
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// verify bit range
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assert(cb.hwif_in.r2.f_no_sign.next[15:0] == '1);
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// verify bit width
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assert($size(cb.hwif_in.r2.f_no_sign.next) == 16);
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// verify unsigned (logic is unsigned in SV)
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assert(cb.hwif_in.r2.f_no_sign.next > 0);
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// verify readback
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cpuif.assert_read('h0, 64'h1FFF_FFFF_FFFF_FFFF);
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cpuif.assert_read('h8, 64'h0000_FFFF_FFFF_FFFF);
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{% endblock %}
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