371 lines
14 KiB
Python
371 lines
14 KiB
Python
from typing import TYPE_CHECKING, Optional, List, Type
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from systemrdl.node import FieldNode, RegNode, AddrmapNode, MemNode
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from systemrdl.walker import WalkerAction
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from ..struct_generator import RDLFlatStructGenerator
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from ..identifier_filter import kw_filter as kwf
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from ..sv_int import SVInt
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if TYPE_CHECKING:
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from systemrdl.node import Node, SignalNode, AddressableNode, RegfileNode
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from . import Hwif
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from systemrdl.rdltypes import UserEnum
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class HWIFStructGenerator(RDLFlatStructGenerator):
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def __init__(self, hwif: 'Hwif', hwif_name: str) -> None:
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super().__init__()
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self.hwif = hwif
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self.top_node = hwif.top_node
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self.hwif_report_stack = [hwif_name]
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def push_struct(self, type_name: str, inst_name: str, array_dimensions: Optional[List[int]] = None, packed: bool = False) -> None: # type: ignore
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super().push_struct(type_name, inst_name, array_dimensions, packed)
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if array_dimensions:
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array_suffix = "".join([f"[0:{dim-1}]" for dim in array_dimensions])
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segment = inst_name + array_suffix
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else:
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segment = inst_name
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self.hwif_report_stack.append(segment)
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def pop_struct(self) -> None:
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super().pop_struct()
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self.hwif_report_stack.pop()
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def add_member(self, name: str, width: int = 1) -> None: # type: ignore # pylint: disable=arguments-differ
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super().add_member(name, width)
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if width > 1:
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suffix = f"[{width-1}:0]"
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else:
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suffix = ""
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path = ".".join(self.hwif_report_stack)
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if self.hwif.hwif_report_file:
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self.hwif.hwif_report_file.write(f"{path}.{name}{suffix}\n")
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#-------------------------------------------------------------------------------
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class InputStructGenerator_Hier(HWIFStructGenerator):
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def __init__(self, hwif: 'Hwif') -> None:
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super().__init__(hwif, "hwif_in")
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def get_typdef_name(self, node:'Node', suffix: str = "") -> str:
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base = node.get_rel_path(
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self.top_node.parent,
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hier_separator="__",
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array_suffix="x",
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empty_array_suffix="x"
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)
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return f'{base}{suffix}__in_t'
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def enter_Signal(self, node: 'SignalNode') -> None:
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# only emit the signal if design scanner detected it is actually being used
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path = node.get_path()
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if path in self.hwif.ds.in_hier_signal_paths:
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self.add_member(kwf(node.inst_name), node.width)
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def _add_external_block_members(self, node: 'AddressableNode') -> None:
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self.add_member("rd_ack")
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self.add_member("rd_data", self.hwif.ds.cpuif_data_width)
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self.add_member("wr_ack")
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def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
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super().enter_Addrmap(node)
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assert node.external
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self._add_external_block_members(node)
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return WalkerAction.SkipDescendants
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def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
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super().enter_Regfile(node)
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if node.external:
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self._add_external_block_members(node)
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return WalkerAction.SkipDescendants
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return WalkerAction.Continue
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def enter_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
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super().enter_Mem(node)
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assert node.external
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self._add_external_block_members(node)
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return WalkerAction.SkipDescendants
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def enter_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
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super().enter_Reg(node)
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if node.external:
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width = min(self.hwif.ds.cpuif_data_width, node.get_property('regwidth'))
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n_subwords = node.get_property("regwidth") // node.get_property("accesswidth")
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if node.has_sw_readable:
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self.add_member("rd_ack")
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self.add_external_reg_rd_data(node, width, n_subwords)
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if node.has_sw_writable:
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self.add_member("wr_ack")
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return WalkerAction.SkipDescendants
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return WalkerAction.Continue
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def add_external_reg_rd_data(self, node: 'RegNode', width: int, n_subwords: int) -> None:
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if n_subwords == 1:
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# External reg is 1 sub-word. Add a packed struct to represent it
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type_name = self.get_typdef_name(node, "__fields")
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self.push_struct(type_name, "rd_data", packed=True)
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current_bit = width - 1
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for field in reversed(list(node.fields())):
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if not field.is_sw_readable:
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continue
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if field.high < current_bit:
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# Add padding
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self.add_member(
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f"_reserved_{current_bit}_{field.high + 1}",
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current_bit - field.high
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)
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self.add_member(
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kwf(field.inst_name),
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field.width
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)
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current_bit = field.low - 1
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# Add end padding if needed
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if current_bit != -1:
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self.add_member(
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f"_reserved_{current_bit}_0",
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current_bit + 1
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)
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self.pop_struct()
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else:
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# Multiple sub-words. Cannot generate a struct
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self.add_member("rd_data", width)
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def enter_Field(self, node: 'FieldNode') -> None:
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type_name = self.get_typdef_name(node)
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self.push_struct(type_name, kwf(node.inst_name))
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# Provide input to field's next value if it is writable by hw, and it
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# was not overridden by the 'next' property
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if node.is_hw_writable and node.get_property('next') is None:
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self.add_member("next", node.width)
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# Generate implied inputs
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for prop_name in ["we", "wel", "swwe", "swwel", "hwclr", "hwset"]:
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# if property is boolean and true, implies a corresponding input signal on the hwif
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if node.get_property(prop_name) is True:
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self.add_member(prop_name)
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# Generate any implied counter inputs
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if node.is_up_counter:
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if not node.get_property('incr'):
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# User did not provide their own incr component reference.
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# Imply an input
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self.add_member('incr')
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width = node.get_property('incrwidth')
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if width:
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# Implies a corresponding incrvalue input
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self.add_member('incrvalue', width)
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if node.is_down_counter:
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if not node.get_property('decr'):
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# User did not provide their own decr component reference.
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# Imply an input
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self.add_member('decr')
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width = node.get_property('decrwidth')
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if width:
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# Implies a corresponding decrvalue input
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self.add_member('decrvalue', width)
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def exit_Field(self, node: 'FieldNode') -> None:
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self.pop_struct()
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class OutputStructGenerator_Hier(HWIFStructGenerator):
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def __init__(self, hwif: 'Hwif') -> None:
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super().__init__(hwif, "hwif_out")
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def get_typdef_name(self, node:'Node', suffix: str = "") -> str:
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base = node.get_rel_path(
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self.top_node.parent,
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hier_separator="__",
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array_suffix="x",
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empty_array_suffix="x"
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)
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return f'{base}{suffix}__out_t'
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def _add_external_block_members(self, node: 'AddressableNode') -> None:
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self.add_member("req")
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self.add_member("addr", (node.size - 1).bit_length())
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self.add_member("req_is_wr")
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self.add_member("wr_data", self.hwif.ds.cpuif_data_width)
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self.add_member("wr_biten", self.hwif.ds.cpuif_data_width)
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def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
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super().enter_Addrmap(node)
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assert node.external
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self._add_external_block_members(node)
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return WalkerAction.SkipDescendants
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def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
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super().enter_Regfile(node)
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if node.external:
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self._add_external_block_members(node)
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return WalkerAction.SkipDescendants
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return WalkerAction.Continue
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def enter_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
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super().enter_Mem(node)
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assert node.external
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self._add_external_block_members(node)
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return WalkerAction.SkipDescendants
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def enter_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
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super().enter_Reg(node)
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if node.external:
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width = min(self.hwif.ds.cpuif_data_width, node.get_property('regwidth'))
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n_subwords = node.get_property("regwidth") // node.get_property("accesswidth")
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self.add_member("req", n_subwords)
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self.add_member("req_is_wr")
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if node.has_sw_writable:
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self.add_external_reg_wr_data("wr_data", node, width, n_subwords)
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self.add_external_reg_wr_data("wr_biten", node, width, n_subwords)
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return WalkerAction.SkipDescendants
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return WalkerAction.Continue
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def add_external_reg_wr_data(self, name: str, node: 'RegNode', width: int, n_subwords: int) -> None:
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if n_subwords == 1:
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# External reg is 1 sub-word. Add a packed struct to represent it
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type_name = self.get_typdef_name(node, "__fields")
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self.push_struct(type_name, name, packed=True)
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current_bit = width - 1
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for field in reversed(list(node.fields())):
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if not field.is_sw_writable:
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continue
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if field.high < current_bit:
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# Add padding
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self.add_member(
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f"_reserved_{current_bit}_{field.high + 1}",
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current_bit - field.high
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)
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self.add_member(
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kwf(field.inst_name),
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field.width
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)
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current_bit = field.low - 1
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# Add end padding if needed
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if current_bit != -1:
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self.add_member(
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f"_reserved_{current_bit}_0",
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current_bit + 1
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)
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self.pop_struct()
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else:
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# Multiple sub-words. Cannot generate a struct
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self.add_member(name, width)
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def enter_Field(self, node: 'FieldNode') -> None:
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type_name = self.get_typdef_name(node)
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self.push_struct(type_name, kwf(node.inst_name))
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# Expose field's value if it is readable by hw
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if node.is_hw_readable:
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self.add_member("value", node.width)
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# Generate output bit signals enabled via property
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for prop_name in ["anded", "ored", "xored", "swmod", "swacc", "overflow", "underflow", "rd_swacc", "wr_swacc"]:
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if node.get_property(prop_name):
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self.add_member(prop_name)
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if node.get_property('incrthreshold') is not False: # (explicitly not False. Not 0)
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self.add_member('incrthreshold')
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if node.get_property('decrthreshold') is not False: # (explicitly not False. Not 0)
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self.add_member('decrthreshold')
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def exit_Field(self, node: 'FieldNode') -> None:
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self.pop_struct()
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def exit_Reg(self, node: 'RegNode') -> None:
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if node.is_interrupt_reg:
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self.add_member('intr')
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if node.is_halt_reg:
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self.add_member('halt')
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super().exit_Reg(node)
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#-------------------------------------------------------------------------------
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class InputStructGenerator_TypeScope(InputStructGenerator_Hier):
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def get_typdef_name(self, node:'Node', suffix: str = "") -> str:
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scope_path = node.get_global_type_name("__")
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if scope_path is None:
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# Unable to determine a reusable type name. Fall back to hierarchical path
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# Add prefix to prevent collision when mixing namespace methods
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scope_path = "xtern__" + super().get_typdef_name(node)
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if node.external:
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# Node generates alternate external signals
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extra_suffix = "__external"
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else:
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extra_suffix = ""
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return f'{scope_path}{extra_suffix}{suffix}__in_t'
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class OutputStructGenerator_TypeScope(OutputStructGenerator_Hier):
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def get_typdef_name(self, node:'Node', suffix: str = "") -> str:
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scope_path = node.get_global_type_name("__")
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if scope_path is None:
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# Unable to determine a reusable type name. Fall back to hierarchical path
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# Add prefix to prevent collision when mixing namespace methods
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scope_path = "xtern__" + super().get_typdef_name(node)
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if node.external:
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# Node generates alternate external signals
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extra_suffix = "__external"
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else:
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extra_suffix = ""
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return f'{scope_path}{extra_suffix}{suffix}__out_t'
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#-------------------------------------------------------------------------------
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class EnumGenerator:
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"""
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Generator for user-defined enum definitions
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"""
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def get_enums(self, user_enums: List[Type['UserEnum']]) -> Optional[str]:
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if not user_enums:
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return None
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lines = []
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for user_enum in user_enums:
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lines.append(self._enum_typedef(user_enum))
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return '\n\n'.join(lines)
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@staticmethod
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def _get_prefix(user_enum: Type['UserEnum']) -> str:
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scope = user_enum.get_scope_path("__")
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if scope:
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return f"{scope}__{user_enum.type_name}"
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else:
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return user_enum.type_name
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def _enum_typedef(self, user_enum: Type['UserEnum']) -> str:
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prefix = self._get_prefix(user_enum)
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lines = []
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max_value = 1
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for enum_member in user_enum:
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lines.append(f" {prefix}__{enum_member.name} = {SVInt(enum_member.value)}")
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max_value = max(max_value, enum_member.value)
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if max_value.bit_length() == 1:
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datatype = "logic"
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else:
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datatype = f"logic [{max_value.bit_length() - 1}:0]"
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return (
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f"typedef enum {datatype} {{\n"
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+ ",\n".join(lines)
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+ f"\n}} {prefix}_e;"
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)
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